Serial Communication

This concerns UART serial communications between the uPD70433 and the uPD780023.
Please explain the detection method for the start bit, character bits, etc., and also the timing with regard to each CPU's UART reception function.

For UART reception, the start bit is used to synchronize bits in received data and for character synchronization as well.
When UART starts a receive operation:

(1) Start of start bit detection
The receive signal is sampled in order to detect the start bit.
The source clock that generates the baud rate (this is the system clock in the uPD70433, and the baud rate generator's 5-bit counter input in the uPD780023) is used as the sampling clock.
Accordingly, the worst case scenario is that detection may be delayed by up to one cycle of the sampling clock.
The switch to start bit detection occurs when the sampling result indicates a low-level receive signal.



(2)Detection of start bit
The baud rate generator's counter starts to operate when a low-level receive signal has been detected.
Start bit detection occurs at the one half position of the bit length that is determined by the baud rate, as shown below.
When re-sampling occurs via this timing and a low-level signal is detected, it is judged as the start bit.



When a high-level signal is detected, it is judged as noise and processing returns to step (1).



(3)Sampling of data
When the start bit is detected and the sampling timing is shifted by 1/2 bit from the start bit's falling edge, subsequent sampling occurs at the bit length determined by the baud rate so that the receive signal can be sampled at the center of the data bit's data.



The processing flow shown above indicates the sampling of data from the receive signal.
In UART serial communications, effects from waveform distortion along the transmission path should be avoided as much as possible by detecting the receive signal at the center of the bit (actually, this is not the precise center in relation to the sampling clock).

What is the allowable baud rate error during UART reception? How can I calculate it?

The allowable baud rate error can be determined by starting sampling at the center of the bit and then seeing where the stop bit position is after repeated shifting of the sampling position has occurred due to baud rate error.

In an ideal case (when there is no delay in detecting the start bit and when no setup or hold times are required for sampling), the error margin at the start bit position is 50% (in other words, the sampling position may shift up to 50% before or after the center).
The allowable baud rate error can be calculated by dividing this by the number of bits before the stop bit.



In an actual case, factors such as the sampling cycle and any setup time or hold time required for sampling must be taken into consideration, so the 50% margin may be reduced to nearly 40%, and this would be divided by the bit length to determine the allowable baud rate error.
(The amount by which the margin is decreased varies among different devices.)
Thus, the value determined in this way is an allowable error that is relative between the transmitting and receiving sides.

These values exist when the receive signal has the ideal waveform.
However, actual waveforms undergo distortion due to the effects of the transmission path.

In such cases, signal transitions are more gradual when they are near the level for start bit detection, and these waveforms are susceptible to noise, so the start bit judgment timing may vary.
Consequently, the margin at the start bit position may drop even below 40%, which would also reduce the allowable baud rate error.
As a result, operation faults can occur if the estimated allowable baud rate error is too large.

Tell me about the basic operation of 3-wire serial communication.

3-wire serial communication is a method of performing communication using transmit data (SO),
receive data (SI), and a transfer clock (SCK).
With this communication method, the side controlling the communication is called the master, and the master controls communication by transmitting SCK.
The other side is called the slave, and the slave transmits or receives data by receiving SCK from the master.


With this method, data can be transmitted and received at the same time and thus efficient transfer can be performed.

Operation outline
When communication is not being performed, SCK is high level.
The master lowers SCK when communication starts.
At the falling edge of SCK, the master and slave output data at the SO pin.
The output data is connected to the recipient's SI pin, so data is fetched at the rising edge of SCK from the master.
By repeating this operation 8 times, the system can transfer one byte of data.


With this method, communication is performed via clock exchanges, and thus the start bit and stop bit are not required like UART.
In addition, data is always fetched using SCK, and thus problems such as correct data not being received due to differences in the transfer rates on the transmitting and receiving sides do not occur.

In this way, the total operation starts from the falling edge of SCK and thus it is necessary to process the transfer results and complete preparations for the next transfer when SCK is high level.

This is the basic operation but some of the new devices have an additional function that enables the SCK logic to be changed (the level when communication is not performed or the transmitting/receiving edge can be changed) or serial operation to be disabled externally.
Also, although the data length is basically 8 bits, there are some devices in which variable-length data of up to 16 bits can be communicated and in which there is a function to transfer multiple-byte data.

Cautions on use
With this method, it is necessary for the slave to complete preparation for transmitting and receiving data (when the slave wants to transmit data, it must finish writing the transmit data and when the slave wants to receive data, it must finish reading the previous data) before the master lowers SCK.
In some cases, a separate handshake signal is required to detect the slave's status via interrupts or polling.
If this order is not followed, data cannot be correctly transferred.

Is it possible to output a synchronous serial signal from the V850 in 16 bits?

This depends on how much error is allowed.
In a general V850 Series product, this corresponds to repeating 8-bit communications twice.
If the CPU processing is fast enough to perform processing between the 1st byte and the 2nd byte, this method can be used.

The V850/SB1 has a serial communication function to enable synchronous communications up to 16 bits in length.
If the CPU processing is not fast enough, we recommend you use this model.

How much is the actual time lag between the 1st and 2nd byte?

Suppose that the internal clock is used and after the write operation for the 2nd byte the next transmission starts within no more than 1.5 clocks.
This means that at there will be an empty space of at least one bit.

                                     Time lag
                                    <        >
           ____      ____      ______________      ____
      SCK      |____|    |____|     ^        |____|
           ____ _________ ___________________ _________
      SO   ____|_________|___________________|_________

                                 *  ^
                                 |  +-Write complete until here
                                 +-Interrupt at this point

At the rising edge of the clock of the last bit, the 2nd byte data write is triggered but if write is delayed more than the falling edge of the next clock (the ^ point of SCK above and the clock not actually falling), that portion will be added.

Which has less time lag: transmitting data using DMA or transmitting data using SIO instead of DMA by transmitting 2 bytes (after transmitting 1-byte data, the 2nd data will be written as soon as SIO is completed)?

The write operation delay is less for DMA. It depends on the timing of the write operation shown above; if writing is completed by that time, both of them are the same.
This differs depending on the clock frequency, transfer frequency, and program.

For serial interface 0 to 3, TO2/TO3 can be selected as the clock.
Is it necessary to set TO2/TO3 to timer output when using them in this way?

No, it is not necessary to set them to timer output.

Is it possible to use TO2/TO3 as the clock for the serial interface and to use them as normal ports?

Even if timers 2 and 3 are used as the serial clock, if the timer outputs are not used, they can be used as ports.

I am using T02 or T03 as the clock output for a serial interface.
Can I use the T02 or T03 output pin as a normal port?

Even when timer 2 or timer 3 is used for the serial clock, TO02 or TO03 can be used as a normal port as long as timer output is not operated.

An interrupt does not occur after data is output using SIO2.

(1) Is the CPU set to the interrupt-disabled state? (2) Check whether the settings for the CSI2 clock is correct.
(3) Is there a problem in the relationship between the serial setting and the startup condition?
Execute debugging after considering the above items.

When communication is performed between two CPUs via UART, does the unstable condition of RXD and TXD at the time of power-on affect communication?

There are no problems as long as the serial signal level is kept high.
However, if it goes low, it may be recognized as a start bit and this may cause a malfunction.
Normally, these serial signals are used as ports prior to the serial setting.
Be careful not let these signals go low at this time.

For example, in the case of the V850/SA1, P14 and P24 function alternately as the TXD signal.
Execute the following settings so that these signals maintain a high level at the time of the initial serial setting:


In addition, to maintain a high level in the input port status prior to this, we recommend that you connect a pull-up resistor to these pins.
(If the setting described in (1) above is entered via bit manipulation, note with caution that the output latch content of other bits may also be overwritten.)

When starting transmission in clock synchronous serial communication, is it possible to write 2 bytes of data, one for the shift register (SIOn) and the other for the transmission buffer register (SOTBn)?

It is not possible to set two bytes initially in the manner you described.
Since CSI in the V850E/MA1 cannot function as double buffer, there is no way to set two bytes of data initially (SIOn is read-only, so it cannot be overwritten).

Data cannot be received in serial transfer. What are the probable causes?

Has the receiving side been started up?
In clock synchronous serial communication, data does not start to be transmitted or received just when the mode is set.

Transmission naturally starts when data is written but reception also needs a startup trigger.
(In the case of reception only, an SIO read is required and in the case of transmit/receive mode, dummy data must be written.)

After setting "transmit/receive mode" on both sides, when transmit data is written to SOTB1 on the transmitting side, it is still in the transfer wait state and when dummy data is written from the reception side to SOTB1 under these conditions, then data will be transferred. Is this correct?

No.
Transmission starts when the master, the transmitting side, writes transmit data to SOTB1.
Here, data transfer starts regardless of the state of the receiving side.

On the other hand, if transfer start has not been set on the receiving side (in the case of transmit/receive mode, dummy data has not been written to SOTB), the receiving side ignores the serial clocks, however many are sent.

That is, the master must start the transfer after transfer start has been set on the slave side.
If this order is not observed, normal transfer cannot be executed.

Does each program have to determine whether the written data is dummy data or true data?

Yes, that is right.
This is determined by a higher-level communications program.
Basically, a receive operation can occur at the same time as a transmit operation during 3-wire serial communications.
Consequently, a program is able to determine whether or not to use received data while completing a transmission.
Normally, FFH is written as dummy data when a receive operation is starting.
Therefore, it is possible to confirm whether the written data is dummy data or true data just by seeing the received data as long as "FFH" is not be used as normal data.

I would like to minimize power consumption, so I do not want to use serial operation mode all of the time.
Is it possible to receive data without starting a receive operation beforehand on the receiving side?

This can be implemented by separately preparing a signal to be used for handshaking.
Add the procedure in which a handshaking signal is prepared as separate from the serial signals, the master outputs a transfer request for the slave before starting the transfer, the slave receives this signal as an interrupt and then informs the master of preparation completion after starting the transfer.
When the slave issues a transfer request, use a handshaking signal to request a transfer to the master once the transfer has started.

In UART transmission processing using the DMA of the V850E/MA1, setting the software trigger bit in the channel control register can be used as the first data transmission trigger. Is this correct? In addition, is it necessary to clear this bit?

Transmission can be started by setting the software trigger bit of the DMA channel control register.
This bit is simply a trigger bit, so it is not necessary to clear it.

Is it necessary to stop the operating clock when changing only the format among the serial port settings?

You do not have to stop the operating clock.
However, you have to stop the operation itself (set TxEn and RxEn to 0).

The following is described in 11.3.3 of the V850E/MA1 Hardware User's Manual (U14359EJ4V0UM00 (4th edition)):


In the explanation above, the operation when TRMDn = 0 for the CSIMn register is described but no description is made for when TRMDn = 1.
Is it possible to receive data when TRMDn = 1 ?

Yes, reception as well as transmission can be executed at the same time when TRMDn = 1.
To start communication when TRMDn = 1, you have to write to SOTBn.
Reading SIOn does not start communication.
On the other hand, when TRMDn = 0, reading SIOn will start communication.
Therefore, SIOEn is prepared for when you want to read data without starting communication.
That is, when TRMDn = 1, SIOEn is not needed. That is why it is not described.

When is PM22 set to 1 when the serial interface is used?

In the V850E/MS1, PM2 becomes FFH when reset is released.
Therefore, if PM22 retains the initial value, you don't have to do anything.
If it is necessary to make a setting, we recommended that you first set the value to P2 and then make the setting before the serial setting is made (to prevent undefined output to pins set as output ports by other bits, the setting should be made after P2 data is set).

When receive data remains at a low level, a reception error (parity error, no stop bit) occurs, but if reception error processing (reading receive buffer (RXB0)) is executed, is it possible to receive data normally afterward?

No.
That action is not appropriate.

The V850E/MS1 UART receives data continuously at the timing determined by the baud rate if a low-level input continues.
Therefore, during this period, reception error occurs continuously.

The answer depends on how this error is processed.
At the last part, it may be interpreted as normal reception (started and changed to high level).
Even if abnormal data is received, there are cases where no error occurs.
Reception processing considering this is required.

0xFF is sent as the UART output after a reset operation.

The initialization procedure seems to be a problem.
The TXD signal and Port 71 share the same pin.
After a reset operation, this pin operates as an input port.

If PM71 is set to output here, the contents of the output latch will be output.
After the reset operation, the output latch is 0, and if it remains as an output port,
a low level (the same level as the start bit) will be output.
This status continues until the output latch is set to 1.
If this period is longer than the time of 1/2 a bit determined by the baud rate, this state is interpreted as a start bit and results in the aforementioned problem.
Initialization should be performed in the following order: set the output latch of P71 to 1 and then set PM71 to output port mode.

Unnecessary data is sent if UART is disabled.

This is because the port shared with the UART output data is set to the output mode.
When performing serial transmission, keep the port shared with the UART output data in the initial status (1: input mode).

Is there any way to detect a break signal (180 to 250ms mark state) sent from the terminal side when starting asynchronous serial communication?

If the PM register of the corresponding port is set to input, the status of the RXD0 to RXD2 pins can be read as a port.

Is there any way to perform transmit/receive completion for the V850/SF1 serial interface (UART)?

Mask the interrupt and check that bit 7 of STIC0 or STIC1 is set by the program.
If it is set, you can determine that the transmission is complete.
Regarding reception, check CSIC1 or CSIC3.
In either case, if it is set, transmission or reception is complete and so reset the flag using the program.

I would like to use transmission interrupts with UART to execute asynchronous half-duplex communications.
What is the timing by which the first interrupt occurs in order to start transmission?

UART's interrupt is a transmission completion interrupt, so it occurs at the stop bit's timing in the transmitted data.

Description In almost all devices, the interrupt related to the transmission for microcontroller-embedded UART is a "transmission completion" interrupt. When using UARTAn in the V850ES/SG2 or V850ES/SJ2 (hereafter referred to simply as the V850ES/SJ2), this is a "transmission enable" interrupt. In either case, just setting transmit as enabled does not trigger an interrupt. When the first data is written, an interrupt occurs when transmission of that data is completed (in the V850ES/SJ2, this interrupt occurs when data has been transferred to the transmit shift register). The second and subsequent bytes of transmit data are written via this interrupt timing. Note with caution that the processing differs between the first bytes of data to be transmitted and the second and subsequent bytes. The V850ES/ME2 includes a FIFO, so a special operation is used for transmit-related interrupts (this operation will not be described here).

After transmission has been set as enabled and the first transmission interrupt has occurred, is it possible to keep triggering an interrupt when each transmit operation is completed?

Yes, that is possible.
In this case, after setting transmission enable status, modify the program to set an interrupt request flag when each transmit operation is completed.
This can trigger the same operation as when a transmission completion interrupt has occurred, and it can be implemented using an interrupt service routine that is common for all data transmit processing.

When the program sets a transmission completion interrupt request flag during initialization, the transmission completion interrupt request flag can be used as a transmission enable flag.
When doing this, be sure to mask transmission completion interrupts in cases where no data has been transmitted.
This will suppress triggering of useless interrupts.

When the IICF0 value is set to "0x01" (to enable operation and generate a start condition after the stop condition is detected), processing gets caught up during the master communication start function's start condition check, and I cannot start communications.
However, this operation is OK if the IICF0 value is set to "0x03" instead of "0x01."

At the controller stage, there is no information to indicate whether or not the I2C bus can be used in its initial state.
Consequently, in conventional controllers, once the controller is started, a stop condition is detected to indicate when the bus can be used (i.e., when a start condition can be issued).
Therefore, if a higher-level program is used to detect whether or not the bus is available and issue a stop condition, then a start condition can be subsequently issued to enable use of the I2C bus.
Such is the case when the IICF0 value is "0x01."

On the other hand, new devices such as V850/ES products have an added function that enables start conditions to be issued without detecting the stop condition.
Use this function (which can be used when the IICF0 value is "0x03") to immediately issue a start condition and enable use of the I2C bus.

I would like to transmit data using CSI00 as the transmit clock and also using timer 50 output, but there is no clock output even when data is written.
My specific settings are as follows.

  (1) __DI();
  (2) TCL50   = 0x04;
  (3) CR50    = 0x11;
  (4) TMC50   = 0x80;
  (5) CSIC0   = 0x06;
  (6) CSIM00  = 0xd0;
  (7) CSI0IC0 = 0x05;
  (8) PMC4    = 0x07;
  (9) __EI();

The reason why the problem is caused is that the bit 1 (TMC501) in the TMC50 register is set to "0" for timer 50 settings.
Set "0x82" for TMC50 instead of "0x80."

(TO50 is the clock for CSI00. If TMC501 is not set to "1", the output F/F is not inverted and TO50 does not change. The TMC50 register should be set for inverted operation of the output F/F, regardless of whether or not TO50 is actually externally output.)

I do not understand how to use the clocked serial interface with automatic transmit/receive function.

When using the clocked serial interface with automatic transmit/receive function, the procedure for continuous transmission of data as the master is as follows.

(1)	Set the CSIAEn bit in the CSIMAn register to "1" to set CSIAn to operation enable status. (This also enables buffer RAM access.)
(2)	Select the serial clock via the CSISn register.
(3)	Set the division ratio for the serial clock via the BRGCAn register to select the serial transfer speed (communication speed).
(4)	Write the target data sequentially, starting from FFFFFE00H in buffer RAM.
(5)	In the ADTPn register, set the number of "(data length to be transmitted) − 1".
(6)	Set the ATEn and MASTERn bits in the CSIMAn register to "1" to select the automatic transfer mode and the master mode.
(7)	Set the TXEAn bit in the CSIMAn register to "1" to enable transmission.
(8)	Set the data transmit interval via the ADTIn register.
(9)	For CSIA0, set bits 4 and 5 in the PFC5 register to "0" and bits 4 and 5 in the PMC5 register to "1". For CSIA1, set bits 11 and 12 in the PFC9 register and bits 11 and 12 in the PMC9 register to "1".

This completes the settings that are necessary to perform automatic transmissions using the clocked serial interface with automatic transmit/receive function.
To start automatic transmission processing, set the ATSTAn bit in the CSIT0n register to "1".

Once automatic transmission processing is started, set the TSFn bit in the CSISn register to "1" to start transmitting the data, which is read sequentially from the start of the buffer RAM.
An interrupt request (INTCSIAn) is issued when the data specified by the ADTPn register has been transmitted, after which the TSFn bit in the CSISn register is cleared to "0".

To send more data, set the new data to the buffer RAM, set the number of the data via the ADTPn register as described above in step (5), and set the ATSTAn bit in the CSIT0n register to "1".

When transmitting and receiving, also set the RXEAn bit to "1" in step (7), set bit 3 in the PFC5 register to "0" in step (9), and set bit 3 in the PMC5 register to "1" (for CSIA1, set bit 10 in the PFC9 register and bit 10 in the PMC9 register to "1").

When the transfer is completed, the received data is stored in the buffer RAM, from where it can be read.

I entered the following settings, but SCKA0 is not output.

    CSIMA = 0xDC;
    CSIS0 = 0x40;
    CSIT0 = 0x01;
    BRGCA0 = 0x00;
    ADTP0 = 0x07;
    ADTI0 = 0x03;
    P5 = 0x07;
    PM5 = 0xc8;
    PMC5 = 0x38;
    PF5 = 0x00;
    PFC5 = 0x00;
    PU5 = 0x00;

There are problems in the sequence and method of these settings.
The range of settings for outputting SCKA0 is:
  - First, set only bits 7 and 6 in the CSIMA0 register.
  - Afterward, set the other bits in the CSIMA0 register.

After setting all of these bits except for ATSTA0:
  - Set the ATSTA0 bit in the CSIT0 register to "1."