Reset

Is the reset release timing of the V850/SB1, SA1 based on only the rising edge?

The reset release timing is based on the level, not the edge.
Reset release is the state obtained when reset is no longer active.

To reset the V850E/MS1 by software, do I have to write code to jump to PC = 0x00000000 ?
Is it necessary to set some registers?

You cannot simply write code to jump to the starting point of the program from inside the interrupt routine.
The program cannot continue correctly afterward.
Set the EIPC register and EIPSW register and then execute the RETI instruction.
This enables subsequent interrupt processing.
Then branch to the initialization area at the start of the program.

What is the minimum pulse width required to maintain a low level at the RESET pin?
Is the reset state entered regardless of the width of the low-level input?

The time required to perform a reset operation correctly is 500 ns.

While the power supply is operating normally with stable clock oscillation, an input that maintains a low level for 500ns or more causes a reset.

If the pulse is shorter than about 60ns, it will be eliminated as noise by the analog delay circuit.
If the pulse is 60ns to 500ns, some blocks inside may be reset and others not.

These states vary depending on the individual device and operating conditions.
Because this status causes uncertain operation, do not input a pulse of 60 to 500ns.
To perform a reset operation, input a pulse of 500ns or more.

Is the internal RAM data held when reset is performed?

When reset is performed during normal operation, RAM data is not guaranteed.

Reset is performed asynchronously to other operations.
Therefore, reset may be performed while RAM is being written.
In this case, writing to RAM may not be performed correctly.
Therefore, when reset is performed during normal operation, RAM data cannot be guaranteed.
This is a matter of the timing at which reset is performed.

No problem occurs if reset is performed while RAM is not being written.
However, if reset is performed while RAM is being written, the reset signal width may become less than the standard value or the address may change while the write signal is on, causing not only the data of the address being written, but also data of other addresses, to be written.
Therefore, the RAM contents cannot be guaranteed.

How long must the clock be supplied before reset is released?

A stable clock must be supplied for at least 500ns before reset is released.
For details, see the data sheet.