Pins..DC Characteristics, Pin Handling

I'm using the V850/SA1 with the external bus specifications.
I want to use a high-resistance pull-up resistor to lower the current consumption.

Is there a design standard?
The operating frequency is 8MHz and the bus wiring length is 30 to 50mm.

Basically, select the value so that the bus level does not change to mid level when the bus is in a high-impedance state.
To avoid this, set a value that maintains a high level even if the bus's leakage current flows through the pull-up resistor.
A value from 50 kΩ to 100 kΩ should be considered.

Naturally, when the resistance is increased, the circuit becomes more susceptible to noise.
The resistance must be lowered to avoid this problem.
These specifications differ among different systems, so the customer's specifications must be checked to determine appropriate values.

"Schmitt trigger input threshold," "High-level input voltage" and "Low-level input voltage" are defined separately.
For example, when the input voltage is Vt+ to 0.75Vdd, how is the logic determined?
("Schmitt trigger has a higher priority" etc.)

Is the high-level input voltage valid before the logic is determined, such as soon after reset?

Please consider that the input-level voltage has the highest priority.
The Schmitt trigger input threshold voltage is for reference only, and is not a rated value.

The following is described on p.62 in the recommended connection of port pins in the V850E/MA1 User's Manual (document number: U14359EJ4V0UM00):

However, most ports are in the input status at the time of reset.
In the actual circuit design, which is correct:

[1] Leave open those pins used as output ports, ignoring the states at the time of reset, or
[2] Make sure to connect to VDD etc. those pins that become input at the time of reset?

The answer depends on many things.
Pins used as outputs should be handled according to how they are used, including the status of the device connected to them.
Unused pins ideally should be treated as [2], but unless the system has a limited operating current (battery operation etc.), the processing in [1] can also be used to make the system compact.

In the Application Note (U15179EJ2V0AN) p.24, it is described that 5V devices can be used as connectable memory if the DC characteristics are satisfied.
Can the output ports be pulled up to 5V.

No.
The device ratings defined in the data sheet clearly state "-0.5 V to Vdd + 0.5 V".

"Satisfy the DC characteristics" when using external memory means that "interfacing with 3 V" is acceptable.
"Satisfy the DC characteristics" as described in the Application Note does not imply that the output can be pulled up to 5V.
Conversely, that's why VOH during write and VIH of SRAM are compared with each other.
Please check again.

In the processing for unused pins described in the uPD70F3107A data sheet, P00..P07 are described as "Input: Connect to VSS".
Is it possible to pull the pins up to VDD when setting the input pins of the I/O ports (initial values)?

Yes, it is OK to pull them up to VDD.
In old devices, when pins were pulled up by resistors, the pin voltage would rise slowly at power-up and be detected as a low-to-high signal change, resulting in the occurrence of an interrupt.
This processing was adopted to prevent this, and still remains in some devices.
In this device, the NMI valid edge is not specified in the initial state and thus this problem does not occur.

Approximately how much pull-up resistance (in Ω) should be used for handling unused pins and for the bus lines?
Are there any recommended values to refer to?
Also, what standards are used to determine these pull-up resistance values?

There are no recommended values to refer to, but the value should be sufficient to maintain the high level input voltage at unused pins even when a high level leakage current is flowing.
For example, when 10 uA of leakage current is flowing and Vdd = 3.0 V, a value of 75 kΩ or less is sufficient to maintain 0.75 Vdd (= 2.25 V), so a pull-up resistance of 75 kΩ or less should be used for Vdd.
As for the bus lines, the total high level leakage current for all devices connected to the bus lines is used as a guide for setting a value to maintain high level.
However, the total current from the connected device's low level leakage and input current plus the pull-up resistance should be compared with the low level drive capacity of the device with the lowest drive capacity, and a resistance value that is about halfway between the high level value and the low level value should be selected as the pull-up resistance applied to Vdd.
Since output from the uPD70F3107 cannot exceed Vdd + 0.5 V, the resistance must not be pulled up to 5 V.

Is there a problem when a high level signal is externally applied to a port when the VDD power of the CPU has not been applied yet?
(Is there an input protection diode in the CPU ?)

This is a problem.
A high level cannot be externally input to a port when VDD is not yet applied.
Voltage can be applied only when the normal power supply is being applied.
If a high level input is applied to a port when the power supply is not being applied and if power is then applied under these conditions, the device may be damaged.

Also note that input protection diodes are not provided from a port in the VDD direction.

In the ROMless version (µPD703100GJ) of the V850E/MS1, operation after power-on reset release is performed as expected, but the address/data bus does not operate at all after additional reset input. Why?

The cause of this symptom is that the WAIT pin is not processed correctly (opened). In the single-chip mode 0, this pin functions as a port by default, but it functions as a WAIT pin in the ROMless mode. The level of the WAIT pin is checked when the first instruction is fetched after power-on reset. If the WAIT pin is open at this time, it happens to be recognized as being at the H level because of the charge that takes place at power-on, and operates correctly without wait operation. However, in the reset input applied after that, the signal level of the WAIT pin depends on the status before reset input. If the WAIT pin is at the L level, therefore, the device enters wait status and bus operation stops immediately after the reset status is released. (It is believed that the WAIT pin is left open in output mode and is discharged because the output data at the time is at L level. As a result, the pin is recognized as L level from then on.) Correctly process WAIT and HLDRQ as alternate-function pins.
Specifically, add a pull-up resistor to these pins.

[Flow of processing alternate-function pins: Example with µPD703100]