Other Peripheral Functions

When connecting external I/O, the I/O ports of the IA2 are used for the /CS signals of external I/O devices for simplification.
That's why the higher-bit port (port DH) of the address bus became unnecessary.
In this case, when DH is set as an I/O port and another external bus port is set as an external bus, do the data bus and control pins work correctly?

Yes, the other external access bus and control pins work correctly.

When an external I/O device is connected to the V850E/MS1, it is inconvenient to execute address decoding.
Is there any method to access the external I/O directly without executing address decoding?

Regarding addresses, the V850E/MS1 memory is separated into 7 blocks, and the type of external device to be connected can be specified for each block.

Therefore, if only a few external memory or I/O devices are connected, one device (memory or I/O) may be connected to each block.
In this case, the /CSO-7 signal output from the device can be connected to CS of the external I/O.

This depends on how many devices are expanded externally and therefore cannot be decided by the V850E/MS1 alone.
(An address is a signal used to distinguish external devices.
If it is not necessary to distinguish devices (that is, if there is only one I/O), address decoding is not required.)

When an external I/O can be accessed directly, is it possible to access 8-bit data bus I/O ?

The V850E/MS1 has a function (bus-sizing function) to specify the bus width as either 8 bits or 16 bits for each memory block.
Using this function, an 8-bit device can be used.

Each port's initial value is undefined, so when operating a port in output mode, can an undefined state be avoided by writing a value to the port in advance?

Yes, an undefined state can be avoided.
In case of setting data after setting the mode, you can avoid having an undefined pin state before data is set.

However, a spike due to gate delay when the output buffer is turned ON may occur after the port is set for output.

In "2.3 Description of Pin Functions" of the User's Manual, it is described that the WAIT signal is sampled at the falling edge of CLKOUT, but when I refer to the timing chart ("Figure 4-5 Example of Wait Insertion" in section 4.6.3) or the data sheet's timing chart, it indicates that sampling is at the rising edge of CLKOUT.
Which is the correct-the description in the text or in the diagrams?

The correct edge is the rising edge.
The description of the WAIT signal in "2.3 Description of Pin Functions" is incorrect.
We apologize for the error.

Note: In latest V850E/MA1 User's Manual, the above error has been corrected.

With I/O alternate function pins, if the port mode of set to input mode by setting the port mode register and the control mode is set via the port mode control register, is it possible to recognize the port input data even when the pins are being operating in control mode?

Yes, if the port mode is set to input mode by setting the port mode register, the pin status can be recognized reading the port, even during control mode.

In the PD70F3032A, when the P111/A1/WAIT pin is used for wait function, can ports 3, 10, and 11 (except the P111/A1/WAIT pins) be used for address output?

No, that kind of operation is not possible.
When using the wait function, use multiplex bus mode.

Also refer to the following FAQ item:
Execution Time: Execution speed [All V850E/MA1]

Please explain the VSWC's role in detail.

Generally, when a CPU is operated at a high speed, problems related to power or noise can occur even in devices that are designed to support such high-speed operations, including even on-chip peripheral I/O operations.
Consequently, the parts that must be operated at high speed and the parts that can be operated at low speed should be set apart by separating the bus.

Ordinarily, the on-chip peripheral I/O are connected to a bus that operates at low speed.
Also, since the various on-chip peripheral I/O are shared among different devices, the need to support CPUs operating at different speeds must also be considered.
Therefore, it becomes necessary to insert several waits to ensure stable operation with the target high-speed CPU and to ensure sufficient access time. With a slower CPU, a number of waits still need to be set to ensure sufficient access time.

In view of these considerations, the V850 includes a VSWC register that is used to set the number of waits during access as the optimum value for the target CPU and its operating frequency. The VSWC register consists of four upper bits and four lower bits, via which the waits used for access setup and the waits related to actual access can be specified independently.

The VSWC register's initial value is 77H, which means that waits equivalent to (7 + 7 =) 14 clock cycles are inserted when accessing an on-chip peripheral I/O.
Accordingly, the total access time is 17 clock cycles when three clock cycles are added as the "no wait" setting.