Memory

Can I perform access to the lower 8 bits of both even and odd addresses using the V850 with only an 8-bit external data bus?

Because there are several types of V850, we have to answer in two ways.

(1) V850E Series (V850E/MS, V850E/MA, V850E/IA etc.)
These devices have BSC registers and the data bus width for each memory block can be set to either 8 bits or 16 bits.
By setting this register to 8 bits, access can be made to that memory block using the lower 8 bits of the data bus.

(2) V850/S Series (V850/SA, V850/SB, V850/SF, V850/SV etc.)
The data bus of these devices is fixed to a width of 16 bits.
Therefore, you cannot simply set the bus to 8 bits.
When an 8-bit device is connected, a bus switching circuit must be externally connected and when accessing odd addresses, 8-bit data must be switched to the higher 8-bit side.
To do this, UBEN and LBEN should be used.
When UBEN is active, select the buffer between the external device and AD8-15 and when LBEN is active, select the buffer between the external device and AD0-7.
Of course, in this case, 16-bit access cannot be made; access can be made only using byte access.

How can I connect a peripheral device to perform byte access to a 1-byte external expansion memory?

If access to external expansion memory is fixed to 8 bits, you can connect the device as is.
However, be aware that if 16-bit access occurs, it does not operate correctly.
It is necessary to manage so that instruction fetches and stack operations other than 16-bit access via instructions do not occur in the external expansion memory.

Can the internal mask ROM be disabled and external ROM used instead?

No.
This product is designed to operate mobile equipment with low power consumption.
The circuit to connect an external ROM increases power consumption, so the product is designed not to attach an external ROM.

The following is described in the MM (memory expansion mode register) setting (on p.77 in the User's Manual):
Which side should port 9 be set, output or input?

You can set it to either side.
By setting the MM register, I/O will be automatically set.
Therefore, when memory expansion mode is used, mode setting register P9 can be set to either input or output.

Tell me about how to set the SDRAM configuration access multiplex width in the V850E/MA1 SDRAM setting?

The configuration of SDRAM is as follows:

- Row address width 11, column address width 8
- Capacity (SDRAM is 512K x 16 bits x 2 banks)
- CPU operating frequency (50MHz)

Set the SCRn register corresponding to the block to connect the SDRAM as follows:

Which address signals can be connected to the bank signals when using 128Mbit or 256Mbit SDRAM?

This depends on the bank configuration of the SDRAM used.

For example, in the case of 64Mbit (4 banks of 1 Mword x 16-bit configuration), 1 bank corresponds to 1 Mword = 2MB.
Therefore, 21 addresses (A0 to A20) are required to perform access to this capacity and the addresses above these addresses are used to specify the desired bank.

That is, A21 and A22 are used to select one of the 4 banks.
The same method is used even if SDRAM is changed and if the capacity of one bank is 4MB, address A22 and above are used to specify the desired bank.

For the V850E/MA1, the capacity of 1 bank is 4MB maximum.
This range must be observed for 128Mbit and 256Mbit as well.

What is the maximum SDRAM capacity that the V850E/MA1 can directly control?

For a device to use all the space, the capacity is 256MB minus internal memory and internal peripheral I/O but the capacity that can be connected by a CS signal is limited, so you cannot directly control that far.

Up to 4MB per bank can be accessed.
The capacity is 16MB if there are 4 memory banks and 32MB for 8 banks.
Up to four of these can be controlled.

As explained above, the capacity varies depending on the SDRAM used.
Therefore, consider the capacity in accordance with SDRAM used.

A11 of the V850 is connected for bank control and the precharge is auto precharge.
Can A11 be fixed to high in this case?

No.
Because the V850 controls precharge, do not fix A11 to high.
The settings, though dependent on the SDRAM used, are as follows:

	V850	SDRAM
Address	A [10:1]	A [9:0]
Precharge selection	A11	A10/AP
Bank selection	A20	BA

SDRAM cannot be written from the V850E/MA1 (1M x 16 SDRAM).
The SDRAM connection is the same as that described on p.176 of the Hardware User's Manual (3rd edition).

- If CBR refresh is enabled, address, data and other signals will not be generated.
- If CBR refresh is disabled, various signals (DQM, RAS, CAS etc.) can be output correctly when written for the first time after initialization. All the data read out are 0xff.

Are the PMCCD settings (SDCLK output mode, SDCKE output mode) complete?
The SELFREF pin may be H level and the CPU may have recognized that SDRAM is in the state of self-refresh.
Set the SELFREF pin to L level.

What are the meanings of TWPRE and TWE shown on the SDRAM write timing chart on p.188 to 190 of the User's Manual.
In addition, are these always provided for each CLK at the time of write access?

These represent the write precharge and the write end cycle, respectively, and they are provided for one clock.

Can the ROMless mode be set for the V850E/MA1 (uPD703106) using the MODE (0-2) pins?

Yes.
For detailed settings, see 3.3.2, "Operating mode specification" in the User's Manual.

In the figure shown in "3.4.4 Memory map" of the User's Manual, the V850/MS1's data space is described as the range from X0000000H to X3FFFFFFH, but in section "3.4.8 Peripheral I/O registers", the address range for peripheral I/O registers starts at FFFFF000H.
How is the memory space configured?

Basically, it is in the same address range.
The V850E/MS1 uses 4 Gbytes of logical memory space, but that does not mean this memory space exists independently. The physical space that can be actually accessed is only 64 Mbytes.

Think of the 4-Gbyte logical space as consisting of 64 blocks of 64-Mbyte physical spaces in a row.
Accordingly, in physical terms, the address range from X3FFF000H to X3FFFFFFH is exactly the same as the address range from FFFFF000H to FFFFFFFFH.
Since the program counter is only a 26-bit counter, when it is used, this range ends at X3FFFFFFH, as is indicated in the figure shown in "3.4.4 Memory map" of the User's Manual.
The figure indicates memory mapping differences among modes, and it clearly shows how the boot area around address 0 is different.

Since a peripheral I/O register consists of 32 bits, when it is used for addressing the data space, any part of the 4-Gbyte logical space can be used, but the most convenient space is within the 32-Kbyte range centered on address 0, in consideration of the LD/ST disp16 instruction that is used for access (including internal ROM access).
Therefore, the address range starting at FFFFF000H was selected.
(See "3.4.7 Recommended use of address space" of the User's Manual.)

Is there any type of DRAM appropriate for the uPD703100?

We no longer recommend a DRAM type for the uPD703100.
(We cannot recommend a DRAM type, as there is a supply-side problem.)
Therefore, use SRAM instead of DRAM when you use the uPD703100.
If you wish to use DRAM, please consider the V850E/MA1 (uPD703103A) for which SDRAM can be used.

When memory read/write is performed in the 16-bit mode, what is the A0 output like?
In the case of an even address, probably A0 = 0 but how is A0 in the case of an odd address?

A0 changes depending on the address to be accessed.
The address changes in accordance with the bus cycle depending on the bus width and data length as described in 4.5.3, "Bus width" in the User's Manual.

- A0 = 0 with 8-/16-bit access to an even address
- A0 = 1 with 8-bit access to an odd address.
- In the case of 16-bit access to an odd address, A0 = 1 for the first 8-bit access and A0 = 0 the second time.

As shown above, A0 = 1 when an odd address is accessed.

In the DRAM controller, is only the column address output in DRAM access?

Yes, the DRAM page function is supported to expedite memory access for the V850E/MS1.
When the second-cycle access is within the page, only the column address will be output.

I have a question about the programmable wait function of the uPD703100A.
Only two wait cycles are inserted when activating CS3 or CS4.
The low-pulse width of RD* and WE* for CS3 and CS4 is 86ns.

In DRAM, the wait cycles cannot be controlled by DWC1 and DWC2.
DWC is a register used to control the wait time for SRAM or ROM etc.;
in DRAM, the wait time is controlled by DRC0-3.

Four types of wait cycles can be set in the DRC0-3 registers, using the DTC register to specify which DRC should be used in each block.
Check to make sure that the BCT register setting is correct (the corresponding bit is set to 00) in the case of SRAM.

When an idle state, TI, is inserted, does CS return to the high state?

Yes, CS returns to the high state in the TI cycle.

A program wait is set after the power is turned on.
Is it possible to change the program wait after the system has moved to application processing?

The settings of the DWC1 and DWC2 registers (program wait) should be made immediately after reset; do not change the values afterward.

The address bus is from A0 to A19.
Is it possible that the memory can be expanded up to 1Mword instead of 1MB using halfword access?

No.
External memory can only be expanded up to 1MB in the V853.
There are 20 addresses and the data bus width is 16 bits, but A0 is used to select the higher and lower bytes.
Therefore, the external memory is 1MB maximum.
However, use the /LBEN or /UBEN signal to actually access the external device.

There are two types of data bus widths for external SRAM, 8-bit and 16-bit. How can I connect SRAMs to the V853 ?

First, for 16-bit SRAM, it is necessary to distinguish the WE signal for each byte (higher and lower 8 bits), that is, WRL and WRH.
(The WE signal corresponding to this is required on the SRAM side.)
If this signal is not connected, when an 8-bit write operation is performed from the CPU, undefined data will be written to the unrelated side.

Next, for 8-bit SRAM, this data results only in even-address data; odd-address data cannot be processed.
When the CPU accesses odd addresses, it uses D8-15 to perform data access.
Therefore, in the case of odd addresses, a bus switching circuit to connect the SRAM data bus to D8-15 of the CPU is required.
In this case, access must be made in 8 bits.
For the operation of the data bus during bus access, see 4.3.2, "Bus width" in the User's Manual.

I want to use the uPD70F3003 in the external expansion mode and set two RAM areas, 100000H - 17FFFFH (512K) and 180000H - 19FFFFH (128K) in block 1 (100000H - 200000H).
How can I set addresses above address A19 (A20 - A23)?

Basically, the V853 can only be expanded up to 1MB externally and addresses A20 and above are not supported.
In the case of the memory map you inquired about, when you access block 0 (internal ROM area), no access occurs for the external area.
Therefore, consider only block 1, which causes external access.

In this case, addresses A20-A23 are not output and thus the CS for each memory is created using addresses A19 and lower, as shown below:

A19	A18	A17	A16
0	X	X	X	Makes CS for SRAM1 active
1	0	0	X	Makes CS for SRAM2 active
1	0	1	0	Makes CS for external I/O active

Because all the addresses are not decoded, when external access is performed, the images of SRAM and external I/O shown above can be seen for each 1MB area.
Therefore, be careful about access to the aforementioned external expansion area block 1 or subsequent blocks.

Regarding SRAM access (p.40 in the Application Note) with the V853, why does a problem occur when using AD0 and writing data at address 0 or above using halfword access and reading data using byte access?

As you inquired, suppose you connect A0 and above of the CPU to A0 and above of SRAM and write to address 0 in halfword units.
Addresses and data are written separately to make it simple.

In this case, the V853 outputs 00000 as the address, outputs data for an even address (e.g. 00) to D0-D7 and data for an odd address (e.g. FF) to D8-D15, and performs a write operation with LBEN and UBEN active (see below).
If seen from the memory side, 00 is written to address 0000 for even-address memory and FF is written to address 0000 for odd-address memory.

V853
~~~~~~~~~~~~|                |~~~~~~~~~~~~~~~~|
     A0-16  |_______0000_____| ADDRESS=0000   |
            |   |            |                |SRAM for even address
     D0-7   |________00______| DATA=00        |
            |   |            |                |
     LBEN   |________________| ENABLE         |
            |   |            |________________|
            |   |
            |   |
            |   |            |~~~~~~~~~~~~~~~~|
            |   |___0000_____| ADDRESS=0000   |
            |                |                |SRAM for odd address
     D8-15  |________FF______| DATA=FF        |
            |                |                |
     UBEN   |________________| ENABLE         |
___________ |                |________________|

On the other hand, let's consider writing the same contents using byte access.
First of all, to write 00 to address 0000, the V853 outputs 00000 as the address, outputs 00 to D0-D7, and makes only LBEN active.
00 is then written to address 0000 for even-address memory (the same result as in the case of halfword access.)

V853
~~~~~~~~~~~~|                |~~~~~~~~~~~~~~~~|
     A0-16  |_______0000_____| ADDRESS=0000   |
            |   |            |                |SRAM for even address
     D0-7   |________00______| DATA=00        |
            |   |            |                |
     LBEN   |________________| ENABLE         |
            |   |            |________________|
            |   |
            |   |
            |   |            |~~~~~~~~~~~~~~~~|
            |   |___0000_____| ADDRESS=0000   |
            |                |                |SRAM for odd address
     D8-15  |________XX______| DATA=XX        |
            |                |                |
     UBEN   |________________| DISABLE        |
___________ |                |________________|

Next, to write FF to address 0001, the V853 outputs 0001 as the address, outputs FF to D8-15, and makes only UBEN active.
FF is then written to address 0001 for odd-address memory.
That is, the address is different from the case of halfword access.
As you can see now, accessing memory using halfword access is different from access using byte access.

V853
~~~~~~~~~~~~|                |~~~~~~~~~~~~~~~~|
     A0-16  |_______0000_____| ADDRESS=0000   |
            |   |            |                |SRAM for even address
     D0-7   |________XX______| DATA=XX        |
            |   |            |                |
     LBEN   |________________| DISABLE        |
            |   |            |________________|
            |   |
            |   |
            |   |            |~~~~~~~~~~~~~~~~|
            |   |___0000_____| ADDRESS=0000   |
            |                |                |SRAM for odd address
     D8-15  |________FF______| DATA=FF        |
            |                |                |
     UBEN   |________________| ENABLE         |
___________ |                |________________|

Next, considering access to address 0002, 0002 will be entered to the address for even-address memory.
That is, address 0001 cannot be accessed for even-address memory.
(0001 is output only when byte access is performed for address 0001, in which case even-address memory is not selected.)
For this reason, only half of the memory capacity can be used.

V853
~~~~~~~~~~~~|                |~~~~~~~~~~~~~~~~|
     A0-16  |_______0002_____| ADDRESS=0002   |
            |   |            |                |SRAM for even address
     D0-7   |________00______| DATA=00        |
            |   |            |                |
     LBEN   |________________| ENABLE         |
            |   |            |________________|
            |   |
            |   |
            |   |            |~~~~~~~~~~~~~~~~|
            |   |___0002_____| ADDRESS=0002   |
            |                |                |SRAM for odd address
     D8-15  |________FF______| DATA=FF        |
            |                |                |
     UBEN   |________________| ENABLE         |
___________ |                |________________|

To avoid such a problem, A0 of the V853 should not be used and A1 and above should be connected to A0 and above of the memory as described in the Application Note.

The resulting V853 memory address and corresponding address of each memory is shown below.
This makes access correct when using either halfword or byte access, and eliminates memory resource wastage.

                            SRAM for         SRAM for 
  V853                    even address     odd address
   00 ------------------------- 00
   01 ------------------------------------------00
   02 ------------------------- 01
   03 ------------------------------------------01
   04 ------------------------- 02
   05 ------------------------------------------02

Does the external chip select signal (CS7) become active when the internal area of the V853 is accessed?

No.
When internal hardware such as the internal RAM is accessed, the external access signal will not be output.