DMA

How can I control a motor with minimum burden on the CPU in the V850 (by using the real-time output function)?

(Common to V850/SA1, SB1, SB2, and SV1)
To control output for which the timing is strictly restricted (such as motor control), use the on-chip timer and DMA functions, combined with the real-time output function.

Suppose that 4-bit real-time output (RTP0-RTP3) is used.
In this case, timer 4 (INTTM4) is used for the output timing.
Because the next data is transferred (DMA transfer) to RTBL at the same timing (INITTM4 is used also for triggering DMA transfer), use Channel 0 (or Channel 1) as the DMA channel.

Assuming that an output pattern is created beforehand in internal RAM (in its lower 4 bits), make the following settings:

(1) Timer 4 generates an interrupt request signal at a regular interval, using the interval timer function.
The interrupt cycle is set as the time of the value of compare register CR40 + 1 count by selecting the timer count clock using the TCL4 register.
However, the timer does not start yet.

(2) The DMA setting is as follows:

DIOA0(or 1) :	Set 3A0H (lower 10 bits of the RTBL address)
DRA0(or 1) :	Set the lower address of the RAM address storing data (the number of valid bits depends on the internal RAM capacity of the CPU).
DBC0(or 1) :	Set the number of data items - 1.
DCH0(or 1) :	Set 19H for the operation mode.

(The internal RAM address is incremented and 8-bit data is transferred from the internal RAM to the peripheral I/O).

(3) For real-time output, first set the ports (P100 to P103) that function alternately as RTP0 to RTP3.

P100 .. 103 :	Initial values
PM100 .. 103 :	Set xxx0000B (set lower 4 bits to output).

Then,

RTPM :	Set 0FH (set lower 4 bits to real-time output).
RTPC :	Set 80H (enables operation in 4-bit, 2-channel mode).
RTBL :	Set next data.

(4) The setting is now complete.
Set TMC4 to 80H (when TM4 and CR40 match, clear & start; no timer output) to start Timer 4.

Now, an output pattern is output to RTP0 to RTP3 at the time interval specified by Timer 4.
Since the initial value and the next data are already set, the data after next is subject to DMA transfer.


Afterwards, output patterns can be generated in succession by resetting and restarting DMA at each INTDMA0 (or 1) interrupt.

In the V850/SA1, I tried to use DMA for UART transmission but DMA did not start when the first data transmission completion interrupt occurred.
The DMA setting is performed after UART transmission is complete.

(All of the following description is common to the V850/SA1, SB1, SB2, and SV1)
The DMA start factor and the status of the interrupt request flag are unrelated.
Set the start factor (transmission completion) to occur after the DMA setting is complete.

Does the first data always have to be written by the program in UART transmission?
Can't I use DMA for the first data transmission as well?

No, you can't.
In this case the DMA start factor is the UART transmission completion signal.
DMA cannot be started by any other method.

When transmitting the second sequence of data after completing transmission of the first sequence of data, is the first data written by program?

It depends on whether transmission of the previous data is complete.
The process for this judgment and setting is shown below.
In this process, it is assumed that the UART transfer rate is not faster than the interrupt response.

When the last data is transferred to UART, a DMA completion interrupt occurs.
At this point, clear the UART transmission completion interrupt request flag.
If there is subsequent data at this point, re-set DMA. (The processing so far can be performed, of course, before the last data has been transmitted to UART.)
If there is no subsequent data at this point, processing ends.
When the data at the next stage is sent, set DMA so that it will start from the beginning of the next data.
When DMA setting is finished, check whether the UART transmission completion interrupt flag is set (that is, check whether transmission of the last data of the previous data transmission is complete).

If the flag is not set, DMA can be started with the transmission completion of the last data in the previous transmission, so the setting is complete.
In this case, wait for the completion of DMA.

If the flag is set, because transmission is already complete, read the DMA byte count register and compare the read value with the set value to see whether those values match.
If the value has been changed, DMA is already operating.
In this case, wait for the completion of DMA.

If the value has not been changed, it means that the DMA setting was not in time.
In this case, change the address and count value so that transmission will start with the second data, then write the first UART data.

Now DMA is set so that it will start after the first data is transmitted.

An outline flow is shown below:

How is data transferred in the DMA transfer mode?

The DMA mode of the V850/Sxx corresponds to "Single transfer" in the V850E.
The bus is released at each cycle.
Whenever a DMA request is issued, data is transferred until TC occurs.

In UART transmission processing using the DMA of the V850E/MA1, can the first data transmission be triggered by setting the software trigger bit of the channel control register?
Do I have to clear this bit after setting?

The first data transmission can be triggered by setting the software trigger bit of the DMA channel control register.
Since this bit is nothing but a trigger, you do not need to purposely clear it.

I want to repeat DMA under the same conditions. However, it starts up only once.

To start DMA, the following conditions must be met:

When DMA is executed once and terminated, the TCn bit is set to 1.
If you try to start DMA in this state, DMA does not start.
When DMA is complete, be sure to read the DMA channel control register and clear the TCn bit.

I want to repeat DMA under the same conditions.
How can I repeat DMA without re-setting the relevant register?

In the V850E series, the DMA source address register, DMA destination address register, and DMA transfer count register each has a dual construction of a master register and slave register.

In a normal DMA operation, the value of the slave register is updated as the DMA operation proceeds.
However, when a terminal count occurs, the contents of the master register are transferred to the slave register.
Therefore, the next DMA transfer is performed under the conditions previously set in the master register.
By setting the MLEn bit of the DMA channel control register, DMA can be executed automatically and repeatedly under the same conditions.

When using these registers under the same conditions as the previous transfer, you do not need to re-set these registers.
You only need to re-set the DMA channel control register (after reading the DMA channel control register and clearing the TCn bit).

To restart transfer with the same settings as previously, which register should be re-set?

If DMA is used via a software trigger, you do not need to re-set registers other than DCHC.
(As described in 6.9 "Next Address Setting Function" in the User's Manual, DSA, DDA and DBC have a dual construction. When DMA reaches the terminal count, the previously set values are restored automatically.)

Change the relevant settings only when you want to change the DMA conditions.
Then set DCHC.

When starting retransfer, is it necessary to read the TCn bit terminal count once immediately before setting DCHC ?

Yes it is.
Be sure to read the DCHC register after DMA is complete.
(DCHC must be read before starting the next DMA because TC = 0 is a condition for starting DMA.)

I would like to pause transfer after issuing a DMA request.
Can I pause DMA by resetting the ENn bit of the DCHC register?

Yes.
In the single transfer mode, DMA can be paused by resetting ENn of the DCHC register.

During a DMA transfer on a 16-bit bus using the V850E/MA1, I believe only even-numbered addresses can be recognized for source addresses and destination addresses.
Is this correct?

Yes, that is correct.
As is described in "(2) Transfer of misaligned data" under section "6.17 Cautions" in the V850E/MA1 User's Manual, if an odd-numbered address is specified, A0 (LSB) is forcibly set to "0" before the transfer is performed.

The V850E/MA1 User's Manual says that DMA transfers from little endian to big endian byte ordering is possible.
However, I cannot find any endian setting in the DMA control register. Is this because the endian ordering is set automatically based on the endian setting in the CS space of the DMA transfer's target memory?

Yes, that is correct.
To be exact, the processing follows the endian setting in the BEC register for each CS space.

The V850E/MS1's User's Manual says (Caution 2 in section "6.7.1 Transfer type and transfer targets")
"In the case of flyby transfer, make the data bus width the same for the source and destination."
Please explain how to do this.

This is done because data conversion from 8 bits to 16 bits (or vice-versa) is not performed as part of flyby transfers.
Consider an example where the CPU performs transfers using a program.
To transfer with 16-bit data width, a space with 16-bit width is accessed via one 16-bit bus access (when the data is aligned to an even-numbered address).
If the same data is transferred to a space with 8-bit width, two bus cycles are used for access.
This is something that cannot be done during flyby DMA transfers.

In the V850E/MS1, DMA transfers to spaces with different bus widths is not guaranteed, even if they are two-cycles transfers, but such DMA transfers to spaces with different bus widths are supported in V850E/MA and V850E/ME devices.

When inserting waits during a DMA flyby transfer between an external I/O and external memory (SRAM), which setting is valid when different memory blocks are used?

For flyby transfers, the block setting on the memory side is valid.

Which setting is used for transfers from external I/O to SRAM and from SRAM to external I/O?

As noted in answer A1 above, this setting is made on the memory (SRAM) side, regardless of the transfer direction.

Can the V850's DMA function be used to transfer data from an external bus to the I2C bus (via internal RAM)?

DMA transfers between the internal RAM and the I2C bus are possible.
However, DMA transfers from an external bus to internal RAM are not possible.

Even transferring between the internal RAM and the I2C bus is not recommended, though, due to issues concerning control of the transfer direction, etc. (for transmissions, ACK signals from the receiving side must be used to determine whether to continue or stop transfers).

In cases where such transfers are possible, approximately what is the maximum transfer speed?

Your question is meaningless (it suggests a misunderstanding).
The DMA transfer speed is greatly faster than the speed required via by the I2C bus (one byte can be transferred every four clock cycles, and the actual transfer rate is about half that much since the CPU operates during each transfer).
The I2C bus's transfer speed determines the DMA transfer speed in this case.