Clock

How long does it take to switch from subclock operation mode to main clock operation mode in the V850/SA1 (uPD70F3017A/AY)?

The main system clock's oscillation stabilization time accounts for almost all of the time period you inquired about, and this time is determined more by the resonator's characteristics than by the device's characteristics.
Up to two instruction cycles are required as the device's clock switching time (refer to "6.3.1 Control registers" in the User's Manual.)

Normally, when the device is operating with the subsystem clock, the main system clock's oscillation should be stopped.
In such cases, the time required for switching is shorter than the main system clock's stabilization time, so this switching time should be set based on the oscillation stabilization time as described above.

In the User's Manual, regarding the clock generation function of the V850E/MA1, there is a description saying,
When using with 1 x fxx only, can a 50MHz clock be input?

No, this usage is not allowed.
In PLL mode, up to 6.6MHz can be input to X1.
A 50MHz clock cannot be input.

In the V850E/MS1 (uPD703100), there is a description saying,
Does this mean CERALOCK can only be used in PLL mode?

Yes, CERALOCK (resonator) can only be used in PLL mode.
When in direct mode, input a clock signal that is generated by an external oscillator.

The description of CLKOUT that appears in "2.3 Description of Pin Functions" in the V850E/MA1 User's Manual says "In single-chip mode 0, because port mode is entered during the reset period, output does not occur from the CLKOUT pin."
Then, is a 50-MHz clock output from the CLKOUT pin during the reset period while in ROMless mode 0?

Yes, it is output.
When in ROMless mode 0, a clock is output from the CLKOUT pin even during the reset period.
For description of the CLKOUT pin's operations during various modes, see the table in "2.2 Pin Status" in the User's Manual.

I want to use a 6.78MHz external clock as the base clock in the V853.
When used in the direct mode, only (0,0) can be set in the CKC register.
So, is the system clock 3.39MHz (half of 6.78MHz)?

Yes, the operating clock frequency during direct mode is one half of the input clock frequency.
Accordingly, when a 6.78-MHz external clock is input, the device operates at 3.39 MHz.

Is it OK to input 5MHz as the X1 input cycle in PLL mode?

Yes, it is.
Because the operating frequency of the uPD70F3003A is 5MHz to 33MHz (when AD is used), there is no problem to input 5MHz as the clock input frequency in PLL mode.
However, an A/D converter cannot be used if the internal operating clock frequency is set to one half of the input clock frequency via CKC register.

Can 6.78MHz from an external oscillator be used as the base clock?

This differs according to the device and the operation mode.
In uPD703003 and uPD70F3003 devices, this operation is enabled only when in direct mode and when not using the A/D converter (it cannot be used when in PLL mode, since the maximum frequency of 33 MHz is exceeded at startup).

In certain other V853 devices (those whose part names end with an "A"), this operation is enabled only when MODE = 0 is set while in PLL mode or when MODE = 1 is set while in direct mode.
When MODE = 0 is set while in PLL mode, the A/D converter can be used only if the CKC register is subsequently set to "02" (operation with fxx).

Tell me the proper use of BUSCLK and CLKOUT for performing clock-synchronized bus control using the V850E/MA1 bus control function.

When CLKOUT is set to output, it is always output.
On the other hand, BUSCLK is usually set to a low level and is output only when a bus access occurs.
In normal use, we advise you to use CLKOUT as the clock.

For EMI protection, I would like to input a clock signal to a CPU that is from a frequency hopping spread spectrum device.
When a 4.8-MHz clock (with about 6% frequency variation) is input from an external source, is operation at 48 MHz possible?

There should be no problem, since 6% variation in a 4.8-MHz signal should be within the rated input range.
Input clock signals are rated according to their cycles, low-level width, high-level width, rise time, and fall time.
There should be no problem as long as these ratings are satisfied.

Is it OK that the clock duty is not 50% when inputting a 4.88-MHz signal to X1 in PLL mode with a 10x multiplication factor?
The actual duty is something like 4/9 or 5/9.

The input clock signal is rated not in terms of duty but rather in terms of low-level width, high-level width, rise time, and fall time.
There should be no problem with your setting, since the low-level width and high-level width are at least 50 ns each.

I am using the V850E/MA1 at 50 MHz.
When high-speed operation is not required, I would like to change the operating clock frequency from 50 MHz to 5 MHz by changing the PLL multiplication factor.
Is it OK to dynamically switch this setting via the CKC register?

There is no problem with dynamically switching this setting via the CKC register.
Note with caution, however, that before modifying the CKC register to the desired setting, you must switch to operation using fxx. (In this case, the operation is already switched to fxx, so there is no problem.)

[All V850E]
Are there any caution points to note when switching clocks in other ways?

Since the CKC register is a specific register, be sure to follow the correct setting procedures (as described below, as well as in "9.3.4 Clock control register (CKC)" in the User's Manual).

(1)  Disable interrupts (set the NP bit of PSW to 1 to prohibit NMIs)
(2)  Prepare data in any one of the general-purpose registers to set in the CKC register.
(3)  Write data from the general-purpose register to the peripheral command register (PHCMD).
(4)  Write data from the PHCMD register to the clock control register (CKC).
(5)  Assert NOP instructions.
(6)  Release the interrupt disabled state (set the NP bit of PSW to 0).

[V850]
I have to wait for PLL to lock when resetting or when recovering from software STOP mode, but is waiting for PLL to lock also required when only the PLL's multiplication factor has been changed?

No, it is not required when changing the PLL's multiplication factor (the PLL does not become unlocked when the clock is switched).

[V850/SB]
What is the procedure for changing the CPU's internal clock from the default setting (Fxx/8) to Fxx?

The PCC register that controls the CPU's clock is a specific register, so follow the procedure described in "3.4.9 Specific registers" in the User's Manual when changing values in the PCC register.

During normal operation (using the main system clock), I would like to use the subsystem clock for the watch function by switching from main system clock operation to subsystem clock operation.
The manual says that the following instruction cycles are required to do this:
(CPU clock frequency before setting / subsystem clock frequency) x 2
But is a wait time still required if the subsystem clock is oscillating even during normal operations?

Yes, the wait time is required.
This wait time is not used to wait for the subsystem clock to oscillate but rather to arbitrate the asynchronous phases of the two clocks that are being switched.

When this wait time is set by software, if the clock is switched early then the subsystem clock will operate during much of the wait time, but the main system clock is also still oscillating, which wastes power.
Is it possible to stop the main system clock before entering this wait period?

It is not possible to unconditionally stop the main system clock before ending the wait period.
Basically, a wait equal to two subsystem clock cycles is sufficient.
Consequently, you may want to wait for a wait period that is set by hardware, such as by:
(1)  Counting two clock cycles using the timer that operates with the subsystem clock
(2)  If that timer is not available, use the watch timer's interval timer function.

I would like to set the V850ES/SG2 to PLL mode and use the 20-MHz CPU clock for operation.
If using an external clock, what should the frequency (MHz) be and which register setting should be used to set this?

The frequency of the externally connected clock varies depending on the PLL's multiplication factor.
For a multiplication factor of 4, use a 5-MHz clock. Likewise, for a multiplication factor of 8, use a 2.5-MHz clock.

The register setting procedure is as follows:
(1)  Set the SELPLL bit in the PLLCTL register to "0" (clock through mode). (This is the default setting.)
(2)  Set the PLLON bit in the PLLCTL register to "0" (stop).
(3)  Set the multiplication factor via the CKDIV0 bit in the CKC register.
(Set "0x0A" for 4x multiplication and "0x0B" for 8x multiplication.)
(4)  Set the PLLON bit in the PLLCTL register to "1" (PLL mode).
(5)  Wait until the LOCK bit in the LOCKR register is set to "0" (lock mode).
(6)  Set the SELPLL bit in the PLLCTL register to "1" (PLL mode).

The CKC register used at step (3) above is a specific register, so be sure to follow this specified procedure when entering settings in the CKC register.

I set STOP mode (RAM hold) to reduce the power consumption in case of power supply voltage decrease, but when a reset occurs due to voltage decrease, the clock starts oscillating again.

In V850E devices, the main system clock's oscillation stabilization time at startup is secured by reset so to set the optimum rise time. Consequently, the main system clock will oscillate whenever there is a reset.

The events that you are reporting are the device's specified operations.
To set RAM hold while operating under a decreased power supply voltage, a reset must be avoided.

Remark
V850/S and V850ES core products are configured so that the main system clock's oscillation is stopped when a reset occurs.

I am having trouble entering STOP mode while the device is operating with the subsystem clock.
How can I do this?

While the device is operating with the subsystem clock, stop the oscillation of the main system clock by editing the MCK bit setting in the PCC register.
Next, enter HALT mode (the subsystem clock's oscillation cannot be stopped).