A/D, D/A Conversion

The first conversion value obtained after A/D conversion was started by setting the ADCS bit of the ADM1 register is not always correct.

This is probably because the comparator, which stops operating when A/D conversion stops, had not started up by the time A/D conversion started.
Either wait for the stabilization time to elapse after setting ADPS = 0 (comparator on), or set ADPS = 1 (conversion including stabilization time).

Note, however, that if the channel is switched and conversion continues with ADSC still set to 1 (conversion enabled), the comparator will already be started up, so the correct value will always be able to be obtained.

Remark
This caution point applies to early V850/S models and some 78K0 and 78K0S models.
It does not apply to A/D converters in V850E models.
A control bit such as is described above has been implemented in the latest device models such as the V850ES/Kx1, and in the latest versions of the V850/SA1 and V850/SB1.
If this bit is set in advance by a certain amount of time or longer, the first A/D conversion result immediately after the start of A/D conversion operation may have sub-standard accuracy.

There is a description saying, "The higher 10 bits of this register hold the results of the A/D conversion" on p.433 of the "V850 User's Manual (Hardware)".
How are the A/D conversion results set in ADCR?

The conversion results are held in the higher 10 bits of ADCR.
Therefore, the bit configuration when ADCR is read is as follows:

Readout data	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Conversion result	bit 9	bit 8	bit 7	bit 6	bit 5	bit 4	bit 3	bit 2	bit 1	bit 0	0	0	0	0	0	0

In the V850/SF1, A/D conversion is repeated at a regular interval for five channels in succession, but I sometimes get an incorrect result (the value becomes that of an adjacent channel).

This may possibly occur for the following two reasons:

(1) Software problem
Did you stop A/D conversion after the conversion of five channels?
The accuracy of the results of the first A/D conversion is not assured.
Ignore the first result data after starting conversion, or do not stop A/D conversion at all.

(2) Hardware problem [Applies to all V850 products]
Is the drive impedance of the circuit that drives the analog input too high?
Judging from the phenomenon, this may possibly be the reason of the trouble.
The A/D conversion circuit samples the analog input to the sampling capacitor and compares the voltage of the analog input with the reference voltage.

Therefore, if the drive impedance that drives the analog input pin is too high, the capacitor cannot be charged sufficiently and the input voltage may not be sampled accurately.

To solve this problem, drive the analog input pin with a lower impedance of less than a few kilo-ohm.
If this is not possible, insert a capacitor for the analog input pin.
When doing this, refer to the anti-noise circuit shown in the User's Manual and also insert a diode to handle the capacitor's charge.

Is the CE bit of the AD converter mode register cleared automatically when AD conversion is complete?

No, even when the A/D conversion operation is completed, the CE bit in the ADM0 register is not cleared (to 0).
However, in the A/D trigger mode, writing of 1 to CE itself is used as a trigger.
It is no problem whether CE is 1 or 0 when operated only in this mode.
CE remains unchanged once it is set.

The CS bit in the ADM0 register operates in a manner similar to the operation you inquired about.
When A/D conversion operation starts, this bit is set (to 1), and it is cleared (to 0) when A/D conversion operation ends.
When repeated A/D conversions occur, such as due to a timer trigger, the CS bit is set (to 1) during each conversion operation and is cleared (to 0) between each conversion operation.

How long does it take from setting CE = 1 (A/D start) in the ADM0 register to storing CS (A/D status).

Three CPU clocks are required from the time CE is set to when CS is stored.