Timers, Counters

In the uPD780984, is it possible to use the 10-bit inverter control timer for interval timer interrupts?
If yes, what is the method for stopping TO70 to TO75 output?

It is possible.
INTTM7 can be generated at every TM7 underflow.
Moreover, to prohibit TO70 to TO75 output, specify the valid edge by setting the TOEDG bit of the TMM7 register, set the TOSPP bit, then input the valid edge of the TOFF7 pin to stop output of TO70 to TO75 (Hi-Z).
Output can also be stopped by INTWDT while the TOSPW bit is set.

I am using the 10-bit interval timer of the uPD78F0988, but since the TO70 to TO75 outputs are not required, is there a method to permanently stop all these outputs?

After setting the TOSPP bit of the TMM7 register to 1 and making the timer operate, input the active edge (the edge indicated by bit 0 of EGP and EGN, which specify the valid edge of INTP0) to the TOFF7 pin. (The valid edge can also be output from P00.)

For details, refer to Remark 1 of the description of TMM7 in the User's Manual.

Can I use the following processing to simply wait a given time interval with the timer without using interrupts?

There is a problem with this method.
If you want to perform timer processing without using interrupts, please mask the interrupt.
You can then wait in an endless loop until TMIF50 is set, but before entering the loop, clear TMIF50.
Also, once TMIF50 is set and the loop is exited, clear TMIF50.

Since no interrupt servicing is required at this time, is it all right not to define the corresponding interrupt function?

Yes, it is not necessary to define the interrupt function.

What is the error of the clock used for the timer, etc.?

There is no error between the internally generated clock based on fxx and the calculated value.
If there is an error, it is caused by the variation of the oscillation clock (main system clock).

Now, judging from the contents of your inquiry, what you are describing is more likely to be a timer interrupt variation rather than a clock error.
The timer interrupt variation is the variation that occurs in the interval from interrupt occurrence until the start of processing, and varies between 7 and 32 clocks depending on the instruction that is currently being executed.
(It's also based on the relationship with the other interrupts. The interval is even longer if the status is the interrupt disabled state.)

In the uPD784031, I am using timer 1 (16 bits) as an external event counter, but it does not respond to the external input signal (INTP0).

There are restrictions regarding the relationship between the external clock of timer 0 and timer 1 and the CPU operating clock.

In each timer, a high period and a low period of 4 times the CPU clock period are required.
When STBC is in the initial status, the CPU clock period is 16 times the supply clock.
In this case, the high and low periods must be 5μs.

SCS0 is also a factor that affects INTP0 sampling, and setting INTM0 and INTM1 is also required to specify the sampling edge.
Please check these points.

In the uPD784215, I want to operate the interval timer (INTTM3) and count the time for 250ms and then generate the INTTM00 interrupt.

Is it sufficient to clear just TMMK0 prior to entering the HALT mode for INTTM00 wait?
Will the count operation not be performed unless TMMK3 is also cleared?
Also, must TMIF3 be cleared every time?

It is not necessary to clear TMMK3.
In this case, INTTM3 is just used for the count clock of timer 0, so it is not necessary to generate an interrupt.
Be sure to mask TMMK3.

Also, if TMIF3 is masked, it will have no effect on anything else, so it can be ignored.
If TMMK3 is cleared, even interrupts that are not required will occur.
In this case, every time an INTTM3 interrupt is acknowledged, TMIF3 is cleared, so there is no need to manipulate TMIF3.

In the description of TMC50 in the uPD789407 User's Manual, there is the following paragraph:

Does "when reading" differ from input capture?

Yes, it does.
This "when reading" means reading timer register 50 (TM50) via the 16-bit counter read buffer.
This sentence says two completely different things.

The first half describes a restriction concerning the capture function.
In this case, naturally, the capture function cannot be used, so timer register 50 is read.

The second half of the sentence describes a restriction on reading.

When using the 8-bit timer of the uPD78F9026A as an external event counter, the count operation is performed using the rising edge.
If the input level from the external count clock is fixed to high, the value of TM00 becomes 1 immediately after operation is enabled (TCE00 = 1).

In the case of counting external events, the specification is such that if the external signal starts with the same polarity as the active edge, this is interpreted as the occurrence of the valid edge and the counter is incremented by 1.

In order to avoid this, set the TI0 pin to a different status than the active edge.

I want to have a fixed frequency and vary the duty in the uPD78F0034A, but sometimes the ON and OFF times are inverted when I check the waveform using PPG output.

There is probably a problem with the timing of writing to CR01.
The output of Timer 0 inverts upon a match with CR00 or CR01.
Therefore, if CR01 is overwritten by a larger value after it is matched, a second match with CR01 will occur in a single cycle, causing the output to invert again, returning to the original value.

Alternatively, when the timer value is smaller than CR01, if a value that is smaller than that timer value is written, a match with CR01 does not occur in that cycle, so matches will occur continuously with CR00. As a result, the output state inverts.

Also refer to the FAQ "No PPG output" immediately below.

I cannot get a stable PPG output. Are there any points I should note other than the PPG output settings?

You need to be careful about the timing of overwriting CR01.
Processing such as the following is therefore required.

(1)	Overwrite CR01 at the timing of the CR00 match interrupt (the timing at which the cycle switches).
(2)	If the new CR01 value is smaller than the previous value, overwrite CR01 at the CR01 match interrupt; if it is larger, use the CR00 match interrupt.

The processing in (1) is easier, but when the value written to CR01 is small, if the timer's operating clock is high, the timer will count up right up until CR01 is written, so there may not be enough time to overwrite CR01.
This does not occur with the processing in (2), but the processing itself is more difficult.
Decide whether to use this processing after considering the timer's count clock frequency, the interrupt time, and the minimum value of CR01.

I set a value to a compare register using the 16-bit timer, but I cannot obtain the desired interval.

Once you have set a value to the compare register, save the sum of that value and the count value of the interval to the memory.
When a match interrupt occurs, write the value saved to the memory to the compare register, add the count value of the interval, and save the new value to the memory again.
A signal with a fixed interval can be obtained by repeating this processing.
Be sure, however, to observe the conditions described in the user's manual or other document when writing a value to the compare register.

[Reference]
This 16-bit timer is a free-running counter.
Therefore, once a value is set to a compare register, that value is compared with the timer value and a match signal is generated if they match.
The timer continues operating.
After this, the next match will occur after the timer has completed a cycle, so the interval will occur at each 16-bit count.
To avoid this, the value set to the compare register must be updated dynamically as described above.

Why does not an interrupt occur when the count value overflows when using TM00 in the 78K0/KB1 as a free-running timer?

In this case, an overflow only causes a flag to be set; an interrupt does not occur.

How can I generate an overflow interrupt?

You can use INTTM010 in place of an overflow interrupt by setting 0FFFFH to compare register CR010.
However, if you are using TM00 as a free-running timer and already using the compare register match interrupt, use the overflow flag during the servicing of that interrupt.

The uPD780078 User's Manual says about 16-bit timer TM0, "pause the count clock when reading the count value."
Does reading the count value cause the count to shift?

No, the count does not shift as a result of being read.
This comment is simply to indicate that the read operation has priority if there is a conflict.

I want to execute PWM output using timers H0 and H1 in the 78K0/KC1.
Is 100% output possible by setting the same value to CMP00 and CMP01?

No, it is not possible.
The value set to CMP01 must be smaller than the value set to CMP00; the same value cannot be set.

I want to operate the uPD780148 at 8.192 MHz and output a square waveform of 2 kHz using an 8-bit timer (TM51).
8.192 MHz divided by 2 kHz is 4096, so I set TCL51 to 07, selected fx/4096 as the timer's input clock, and set CR51 to 1.
However, the output was 500 Hz.

You need to consider the following two points.

• The timer (TM51) will count up from 0 to the set value of CR51, so you need to set CR51 to a value that is the number of counts of the period to be counted minus 1.
• The period counted by the timer is either high level or low level.
  Therefore, the time of the output cycle will be double that of the timer count.

With your setting, the output will be inverted after the timer counts 2 cycles of the 2 kHz input clock (CR51 set value + 1), so 1 cycle of output becomes 4 cycles of the input clock, thus 500 Hz.

To obtain a 2 kHz output, you have to select an input clock frequency that is at least 4 times the desired output.
Therefore, please select fx/256, i.e., 32 kHz, for TM51.
A 2 kHz output has a 16-clock cycle, so the high-level (or low-level) period is 8 clocks.
For TM51 to count a time equivalent to 8 clocks, set CR51 to 7 (= 8 - 1).