Serial Communication

What serial interface is built in a microcontroller?

The following serial interfaces are provided to a microcontroller.
Of these, (1) to (3) are mainly used.
(1) can be connected to RS-232C used for PCs, by converting signal levels.
(2) and (3) are mainly used for on-board connection of microcontrollers and a microcontroller and an external EEPROM.

(1) UART (Universal Asynchronous Receiver and Transmitter)
This is the most commonly used interface.
It can transfer data of 7 or 8 bits and can check errors by using parity.
In addition to this interface, some microcontrollers support
- Infrared communication function
- LIN (Local Interconnect Network) interface function
Some UART interfaces have a function to successively transmit multiple data, in addition to transmitting individual data.
(Also refer to "Selecting serial I/F" and "Basic operation of start-stop synchronization".)

(2) Three-wire serial interface
This interface uses three signal lines, a serial clock line and two data lines, and can transfer 8-bit data bidirectionally at relatively high speeds.
Data can be selectively transferred starting from the lowest or highest bit.
Some microcontrollers also support
- Functions compatible with SPI (Serial Peripheral Interface)
- Functions to transfer multiple data
(Also refer to "Selecting serial I/F" and "Basic operation of three-wire serial communication".)

(3) I2C bus interface
This interface can communicate with two or more units, using two signal lines and in bus format.
Some types of this interface support a single master, while others support multiple masters (most of the latest devices support multiple masters).
(Also refer to "Selecting serial I/F" and "I2C bus".)

(4) SMB (System Management Bus)
This interface uses a bus using two signal lines, such as the I2C bus, for communication, and, depending on the setting, is compatible with I2C.
Some devices are equipped with this interface.

(5) CAN (Controller Area Network)
This bus is mainly used in automobiles.
Several types of interfaces are available depending on what standard is supported.

(6) IE-Bus
This is also mainly used in automobiles and covers transfer rates lower than those of CAN.
An IE-bus controller provided to a microcontroller is usually of sub-set version.

Serial communication
A microcontroller (MCU: Micro Control Unit) is not only incorporated into a system but also, in many cases, used in combination with two or more other microcontrollers.
In some applications, a microcontroller is connected not only to other microcontrollers but also to external I/O and memory.
Serial communication is often used in these applications.
This section explains serial communication used for communication between one microcontroller and another, or between a microcontroller and an external I/O or memory.

I'm planning on developing a system in which two or more microcontrollers communicate with each other serially. Which serial I/F should be used for communication between microcontrollers?

The first thing that must be considered is whether there is only party or multiple parties of the serial communication.
Serial communication is usually executed on a one-to-one (point-to-point) basis.
To communicate with two or more parties, as many serial channels must be prepared.
In the example shown below, microcontroller 1 communicates on a one-to-one basis with microcontrollers 2 to 4.
In this case, microcontroller 1 needs three channels of serial I/F.
However, only one channel of serial I/F is enough for microcontrollers 2 to 4.



To establish communication among microcontrollers 2 to 4, as many serial channels are necessary.
In such a configuration, communication can be simultaneously executed.
If the number of communication parties increases, however, as many serial channels are necessary.
If the number of parties to be connected is few, then one-to-one communication is recommended.
The representative serial communication functions of this method are

• Start-stop synchronization (using UART)
• Three-wire serial communication (using SIO or CSI)

The start-stop synchronization function can easily realize relatively low speed communication, and the three-wire serial communication function is suitable for communication at relatively high speeds.
For start-stop synchronization, refer to "Basic operation of start-stop synchronization".
For three-wire serial communication, refer to "Basic operation of three-wire serial communication".

If there are many communication parties, using a serial bus in bus format is simpler and more convenient.
By using a serial bus, data can be transmitted by one bus, so that the number of signal lines and serial I/Os can be decreased.
However, the transfer rate of the serial bus that can be used with an MCU is slow.
In addition, the transfer rate is further slowed because one bus is shared.



A representative serial communication function of this method is

• I2C bus (using I2C bus controller)
  (IE-Bus and CAN are also used in specific fields.)

For the I2C bus, refer to FAQ of "I2C bus".

In addition to these two, an SPI that establishes communication between one microcontroller with two or more microcontrollers by extending the function of a three-wire serial interface that is originally intended for one-to-one communication.
The basic concept in this case is illustrated below.
The signals used to transmit the actual data are the same as those for three-wire serial communication.
Signals of the same function are connected to microcontrollers 2 to 4 that serve as slaves.
As it is, serial output signals contend with each other.
A chip select function is thus added to select one of the signals.
As a result, microcontrollers other than the one selected make the serial output signals go into a high-impedance state and do not receive or transmit data.
Microcontroller 1, the master, selects one of the parties of communication by using a port.
It usually performs communication by the same operation as that of a three-wire serial interface.



Taking the above differences in functions and communication speed, select a serial communication method.

Some serial communication functions provided to microcontrollers have a clock while the others do not. What is the difference between these?

For serial communication, data, for example, of 1 byte is broken down and 1 bit is transmitted at a time.
The data transmitted in this way must be restored to the original data at the reception side.
At this time, the original data cannot be restored unless it is known which signals of those transmitted are valid data and from which to which is a cluster (byte data).



(a) Synchronous communication
A simple method to indicate which data is valid is to transmit a signal that indicates the valid data.
The signal for this purpose is a (serial) clock signal.
If serial data changes at the falling edge of a clock, such as in the example of synchronous communication shown below, the correct data can be captured at the rising edge of the clock.



As a result, the position of the correct data (bit) is clarified.
In other words, bits are synchronized.
A way of communication that synchronizes bits by transmitting a clock signal is called a (clock) synchronous communication.
In most cases, the internal synchronous communication function of a microcontroller transmits a clock only when transferring data.
Consequently, unless the sequence of starting is incorrect, which data is the beginning and up to which data constitute data of a character can be made clear (this is called character synchronization or byte synchronization).
By this method, the transfer speed is determined by the clock signal that is simultaneously transmitted with data, and therefore, the transfer speed can be set relatively freely and to a high value.
Because a clock is transmitted, however, data may be destroyed if even one of the clocks is not correctly received.
When reception is started from the middle of data transmitted, therefore, the bit position of the data may be shifted, and after that, the correct data may not be able to be reproduced (received).
To avoid this situation, it is necessary to initialize the serial controller when communication stops.
For further information, refer to "Handshake".

[Remark]
A clock is continuous for synchronous communication that is used as a general communication mode.
Consequently, it cannot be identified from which to which is the data.
By transmitting a synchronization character, therefore, character synchronization is established so that it can be clarified from which to which is the data.
By this method, however, the synchronization character is transferred when data is not transferred.
In this way, the operation differs even by the same synchronous communication method.

(b) Start-stop synchronization communication (asynchronous communication)
Start-stop synchronization communication (asynchronous communication) is a method of communication by which to transmit data without using a serial clock.
Only data signals are transferred by this method, the transfer rate at the transmitter side must be matched that at the receiver side in advance.
As a result, the data (bit) intervals are determined.
However, the timing up to which is the correct data is not known as it is.



To reproduce the correct timing from a data signal itself, a part that determines the timing, as well as the data part, is necessary.
Therefore, control parts, such as start bit and stop bit, are appended to the data signal.



As a result of appending a start bit to the beginning of serial data as shown above, the beginning of the data signal is clarified so bit synchronization and character synchronization are enabled.
To make the start bit of each character valid, it is necessary to append a stop bit to the end of the data, so that the serial data once goes high when transmission has been completed.
The serial data must be kept high when there is no communication data.
To detect the start bit in the correct timing, the receiver must monitor the serial data at an interval shorter than the bit interval.
Consequently, the communication speed cannot be made as high as the speed of synchronous communication.
Basically, there is no difference between the start bit and a data bit that is 0.
If reception is started in the middle of data being transmitted, therefore, incorrect data is received.
In this case, if reception is started in the middle of a part of one character that does not have data, the following data can be correctly received.

[Remark]
Basically, the transfer rate of the transmitter must match that of the receiver for start-stop synchronization communication.
However, the transfer rate can be matched by sending specific data (usually, 55H) at the beginning of communication.
The receiver can also calculate the transfer rate by measuring the signal width of the serial data with a timer/counter.
If the transfer rate is limited to some extent, for example, 9600 baud, 19200 baud, or 38400 baud, data is received at the highest transfer rate thinkable.
The transfer rate is inferred from the number of data received and the value of the data.

Introduction
For internal serial communication of a microcontroller, handshaking (protocol) indicating whether communication is ready, except the serial bus, must be prepared by the application side.
This section introduces a typical phenomenon that occurs as a result as Q1, and its countermeasure, a handshake, as Q2.

Communication is attempted between two microcontrollers using a three-wire serial interface, but cannot be correctly performed. As a result of checking the waveform, it was found that the master transmits correct data but the data cannot be correctly received. The slave does not transmit the intended data. In addition, one transfer end interrupt of the slave that should occur does not occur. Why does this happen? If the transfer rate is increased, the symptom gets worse, and the shortage of transfer end interrupt increases.

This phenomenon occurs because the slave is not ready for communication when the master starts communicating.
The phenomenon that is occurring is explained by using the timing chart below.
When the master starts transmission, the clock (SCK) falls and the first data (B0) is output.
However, the slave misses this data because it is not yet been ready for communication.
After that, the slave starts operating but, in the example below, it determines that B1 is the first data.
When the master completes the first data transmission by outputting up to B7, the slave is still waiting for the next because it thinks that it has not received all of the data.
When the master outputs the next data, B0, the slave receives this data as part of the first data, and generates a transfer end interrupt.
The first data the slave has received is, therefore, B1 to B7 and B0, which is different from that transmitted by the master, B0 to B7.
In other words, the data transmitted by the master and the data received by the slave is shifted 1 bit.
This situation lasts to the end.
If the master completes transmitting n data, the slave is therefore still receiving the nth data.
Consequently, only n-1 transfer end interrupts occur.



If the time since the slave has received data until it gets ready for receiving the next data is longer than the transfer rate of the serial data, the shift is further expanded.
This is illustrated by the timing chart below.
In this chart, the slave completes the first reception when the master transfers the first bit (B0) of the next data.
Because of the processing time of the slave, the slave starts reception at the second bit (B1) of the data from the master and receives the third bit (B2) as the first bit.
As a result, the bit shift between the master and slave substantially increases.



When slave transmits data, a bit shift occurs and, consequently, the correct data is not transmitted.
As shown in the example below, the slave is not ready for transmission when the master starts reception.
Consequently, the first bit the master receives is the SO pin status of the slave at that time.
After that, the slave outputs transmit data, but the master receives data starting from the second bit (B1).

What measure should be taken?

Add a handshake signal.
(In addition, data for checking may be added to the data itself to improve the reliability of communication, but this is an auxiliary method.
Basically, generation of differences in timing should be suppressed.)
To transmit data, it is usually necessary to check whether the other party is ready.
However, such a function is not provided to serial communication signals themselves (except the serial bus), and therefore, a signal (called a handshake signal) must be separately prepared.

[Example of control signals]
For this purpose, the following signals are used by modems.

RTS (Request to Send)
CTS (Clear to Send)

The RTS signal is asserted when data is to be transmitted, notifying the receiver that the transmitter wishes to transmit data.
The receiver, when it is ready for reception, asserts the CTS signal, notifying the transmitter that it may transmit data.
The sequence at this time is illustrated below.



These handshake signals used by modems cannot be used for delicate control of communication as it is.
Therefore, the definition of the signals is changed for local communication between microcontrollers, as follows.

RTS:	The master outputs a low level when it wishes to transmit data. The slave judges the falling edge to be a request for transmission, and the rising edge as the end of transmission.
CTS:	The slave outputs a falling edge when it is ready for reception. (The slave outputs a high level when it has received data once, and outputs a falling edge when it has been ready for receiving the next data.) The master transmits data of one character when it detects the falling edge of this signal.

The above connection is made to process these signals.
The master outputs the RTS signal by using a port, and the slave monitors this signal by using an edge detection interrupt.
Because the RTS signal uses both the rising and falling edges, the edge detection interrupt and port are used to read the status of the port.
The CTS signal uses only the falling edge.
Therefore, the signal output by the slave through port is monitored by the master by using a falling edge detection interrupt.

[Transmission processing procedure using control signals]



The above processing procedure is explained as follows.
It is assumed that the ports of both the master and slave are high in the default status.
(1) The master sends the RTS signal (falling) to the slave through port before transmitting data, and waits for permission for transmission from the slave.
(2) The slave checks the transmission request from the master by generating the edge detection interrupt and checking the level of the RTS signal, and prepares for reception (starting reception) (even if the slave starts reception, actual transfer is not executed unless the master sends SCK (serial clock)).
(3) The slave sends the falling edge of the CTS signal to the master, notifying the master that the slave is ready for reception, by outputting a low level to the port when it has started reception.
(4) The master transmits data when it has detected the falling edge of the CTS signal from the slave.
(5) The slave receives data from the master.
(6) The master waits for the transmission end interrupt.
When transmission is completed, the master judges whether it should transmit the next data.
If the next data is present, the master returns to waiting for the falling of the CTS signal in (3).
(7) The slave outputs a high level to the port, raises the CTS signal, and processes the received data when it has completed reception.
(8) The master, when it has completed transmission, raises the RTS signal, notifying the slave that the master has completed transmission.
(9) The slave processes the received data, and completes transfer when it has confirmed that the RTS signal from the master has risen, by the edge detection interrupt and level checking.
If the RTS signal does not rise, the slave returns to the next reception.

In this example, the RTS signal is used.
If the slave is always ready for reception and there is no problem (however, the actual communication has not yet been executed), the RTS signal is not necessary.

Transmission by the slave can also be realized by similar processing.
In this case, the RTS signal means a request for data from the slave, and the CTS signal means that the slave is ready for transmitting the data.

Some devices can write the next data before transmission is completed while the others cannot write the next data until transmission is completed. Why?

This is because of the difference in configuration of the serial transmission block.
To execute serial communication, a parallel-to-serial conversion register is necessary because parallel data is written and output on a bit-by-bit basis.
If data is directly written to the conversion register and is converted into serial data, the structure is simple.



With this configuration, however, the conversion register is occupied while serial data is transmitted, which means that the next data cannot be written until all the bits have been transmitted.



To transmit multiple data, therefore, the following time is necessary.

Effective transfer time = Actual transfer time + Time from completion of transfer to preparation of next data

Even if the effective transfer rate is to be quickened, there is a restriction of the processing time of the CPU.
For improvement, some devices use a double buffer configuration that uses a register for writing, in addition to the conversion register.



With this configuration, the CPU writes data to the write register.
The data written to this register is transferred to the conversion register when the conversion register is empty.
The difference in timing between these two configurations is illustrated below.



If only the conversion register is used, the next data is written to the register when transmission has been completed.
In contrast, using the double buffer configuration can give the CPU sufficient processing time because the next data can be written even while the first data is transmitted.

I want to successively transfer serial data. How long does it take the CPU to read data after the data has been received?

This depends on the difference in the configuration of the serial transmission block.
The block diagram of the reception block of a general three-wire serial interface is shown below.



With this configuration, the received data remains in the conversion register and must be read before the next data is transferred (in most of the cases, reading is the condition of starting the next reception for an ordinary reception-only operation).
If a slave receives data, it cannot correctly receive the next data unless it reads the first data before the next data is transferred (also refer to FAQ of handshaking).
Consequently, the period of time from the rising of the serial clock indicating completion of reception to the falling indicating the start of the next transmission is very short.
If this configuration is not sufficient, use a three-wire serial channel having an automatic transmission/reception function.



On the other hand, the general UART for start-stop synchronization communication is of double buffer configuration and has a read register in addition to a conversion register that converts serial data into parallel data, as shown below.



An example of timing with this configuration, where data is 8 bits long and transmitted without parity and with 1 stop bit, is shown below.



As shown in this example, the received data may be read within the time of one character until reception of the next data is completed, which gives sufficient time of processing.

For full-duplex and half-duplex communication, refer a communication-related glossary.

Communication may be executed in full-duplex or half-duplex mode. Does the internal serial interface of a microcontroller support full-duplex communication?

Of the internal serial interfaces of a microcontroller, UART supports full-duplex communication.



Basically, a serial interface in bus format, such as an I2C bus, can send data in only one direction at a time, which means it can communicate only in the half-duplex mode.



A three-wire serial interface can bidirectionally send data at the same time, and therefore, is capable of full-duplex communication.



It cannot, however, transmit and receive data independently like UART, and transmission and reception are executed in synchronization with a serial clock (SCK).
This means that transmission and reception must be executed totally at the same timing.
When full-duplex communication is executed by using a transmission/reception mode, therefore, the received data may become invalid.
The following example shows a case where transmit data from the slave does not come when the master transmits data.
Usually, the possibility that the two have data to send at the same time is low, and therefore, the probability that such an operation may be performed is high.
To prevent this operation, data of all 1 or all 0 should be ignored as invalid data.

I am executing serial communication between the uPD70433 and the uPD780023 using UART.
Please give me details about the detection method and timing, etc., of the start bit and character bits during UART reception by each CPU.

In the case of UART reception, a start bit is used to synchronize the bits and characters of the receive data.
A UART reception operation occurs as follows.

(1) Detection of start of start bit
The reception signal is sampled in order to detect the start bit.
The original clock that generates the baud rate is used as the sampling clock (this is the system clock in the case of the uPD70433 and input of the baud rate generator's 5-bit counter in the case of the uPD780023).
It is therefore possible that a delay of up to one cycle of the sampling clock may occur.
If the sampling result is low level, the operation moves to start bit detection.



(2) Start bit detection
Once the change of the reception signal to low level has been detected, the baud rate generator
counter starts operating.
Start bit detection occurs at the position of half the bit length determined by the baud rate,
as shown below.
Sampling is performed again at this timing, and if the level is low, it is judged as the start bit.



If the level is high, it is judged as noise, and the processing returns to (1).



(3) Data sampling
Because the sampling timing is shifted by half a bit from the falling edge of the start bit at start bit detection, by subsequently sampling at each bit length determined by the baud rate, the reception signal can be sampled in the center of the data of the data bits.


Data is therefore sampled in the above flow.
Because UART detects the reception signal in the center of the bit in this way
(although it is not exactly the center due to factors related to the sampling clock),
effects from waveform distortion on the transmission path can be minimized.

What is the allowable baud rate error in UART reception? How is this error calculated?

The allowable baud rate error is determined by where the stop bit position shifts to when shifts in the sampling position due to the baud rate error have accumulated after sampling was started at the center of the bit.

Theoretically (when there is no delay of start bit detection and setup and hold time is not required for sampling), the margin at the start bit position is 50% (i.e., a 50% shift either side of the center is acceptable).
The allowable baud rate error is calculated by dividing this by the number of bits until the stop bit.



Actually, however, it is necessary to add sampling cycles or data sampling setup and hold time, so the margin drops from 50% to 40%.
This is then divided by the bit length to determine the allowable baud rate error. (The extent to which the margin decreases differs depending on the device.)
The value thus obtained becomes the relative allowable error of the transmission and reception sides.

Note, however, that these values apply to an ideal reception signal waveform.
In reality, the reception waveform is distorted by effects from the transmission path.
In this case, changes in the signal in the vicinity of the level at which the device judges the start bit become dull and the device becomes vulnerable to effects from noise, leading to variations in the judgment timing.
Consequently, the 40-odd percent margin at the start bit position becomes even smaller, and the allowable baud rate error is reduced by this amount.
Therefore, if the allowable baud rate error is estimated at quite a large value, a malfunction may occur.

Could you describe the basic operation of 3-wire serial communication?

3-wire serial communication is a communication method that uses transmit data (SO), receive data (SI), and a transfer clock (SCK).
In this communication method, the device that controls communication is called the master, and the master controls communication by outputting SCK.
The device on the opposite side is called the slave.
The slave receives the SCK from the master and transmits/receives data.



Since transmission and reception are performed simultaneously, efficient transfer can be performed.

Operation Outline :
When communication is not performed, SCK becomes high level.
When the master starts communication, it makes SCK low level. At the falling edge of SCK, the master and the slave output data on their SO pin.
Since the output data is connected to the SI pin, it is loaded when the master makes SCK high level.
One byte of data can be transferred by repeating this operation eight times.



Since the clock is used for data transfer in this method, there is no need for a start bit and stop bit as for UART.
Moreover, since data is always loaded at SCK, failure caused by a different transfer rate between the transmitting and receiving sides never occurs.

In this way, the transfer operation starts from the falling edge of SCK, so it is necessary to process the transfer result and complete preparations for the next transfer while SCK is high.

This is the basic operation.
In some of the new devices, however, a function to change the SCK logic has been added.
Using this function, the level when communication is not performed as well as the transmit/receive edge can be changed.
Serial operation can also be prohibited externally.
Also, although the data length is basically 8 bits, there are some devices in which variable-length data of up to 16 bits can be communicated and in which there is a function to transfer multiple-byte data.

Usage Cautions :
Using 3-wire serial communication, the slave must have completed transmit/receive preparations (completed transmit data write when the slave wants to transmit data, or completed reading the previous data in the case of reception) before the master outputs SCK (making it low).

Consequently, be sure to prepare a separate signal for handshaking and enable detection of the slave-side status (ready) by means of an interrupt or polling from the master.
If this order is not followed, data cannot be correctly transferred.

[These contents are common to the 78K/0 Series, 78K/0S Series, and 78421X Subseries.] When using a serial channel in these microcontrollers, port settings are required. Serial channels and I/O ports are shared as alternate functions. When executing serial communication, port mode and output latch data must be set. Regarding signals that also serve as output signals in particular, it is necessary to set the port to the output mode and set the data determined for the port output latch (which depends on the device and signal). If these settings are not performed, the transmission end interrupt is output even though the data has not been sent.

Case 1 :
In the uPD784216A, serial channels 0 and 1 are set to the 3-wire serial I/O operation mode, but the serial clock is not output correctly.

Please check that the data in the output latch of P22 or P27 (alternate function of SCK ) is 0.
It must be 0.
The port output latch and alternate function signal (here, the clock) are input to an OR gate and the output signal of the OR gate is output to the pin.
Therefore, when the output latch is 1, the pin is fixed to high. Set the P2 output latch to 0.

Case 2 :
In the 78K/4, I am using 3-wire serial communication, but the data is not correctly output.

There is a problem in the setting of P21 (the alternate function of the serial data output).
The serial output and the P21 output latch output are input to an AND gate and the result of the AND gate is output to the output pin. Therefore, P21 must be 1.
Since the initial value of P21 is 0, the pin level remains low. Set P21 to 1.

Case 3 :
In the uPD780034A, UART reception is possible, but transmission cannot be performed.

This is likely to be because of the setting of the alternate function of the UART TxD signal.
Please set P23 and P24 as follows.

Case 4 :
In the uPD78F0034A, I am using 3-wire serial I/O, but the serial clock and data do not operate.

Please check that the output latch (alternate function of SCK30 and SO30) is 0.
It must be 0.
If the output latch is 1, no signal is output externally, but the operation itself is ended and the interrupt request flag is set.

Case 5 :
Reception is performed using UART in the uPD789022, but data cannot be acquired by the receive buffer register (RXB00).

PM20 is set to 1, but is PM22 (RxD pin) perhaps not set to 1 (input)?
When the value of PM22 is 0, the pin changes to output and normal data cannot be received.
Please check this point.

In the uPD780078, how is the slave mode/master mode switched?
Is the slave mode set by setting bit 5 of serial operation mode register 1 (CSIM1) to 1, and the master mode set by setting that bit to 0 ?

No, this is incorrect.
When the external clock is selected by setting CKS12 to CSK10 bits of the CSIC1 register to 1, the slave mode is selected.
In all other cases, the master mode is selected.
Please refer the uPD780078 User's Manual for details.

The device that outputs the transfer clock (the device for which the clock source is internal), in other words the device that controls communication, is the master, and the device to which the clock is externally input is the slave.

When the slave mode is selected and SSE1 = 0 (don't use) is set, is the reception operation normal?
Can a transmission operation be started by writing to SOTB1 ?

When SSE1 = 0, normal 3-wire operation is performed.
Even during normal slave operation, transmission is not started simply by writing data to SOTB1.
In this case, transmission starts only when the clock is input from the master, after writing data to SOTB1.

I am using serial interface channel 2 as UART, but following reset, 0xFF is the first value that is output.

There is a problem with the initialization procedure.
The TxD signal is shared with port 71, and after reset, it functions as an input port.
If PM71 is set to output, the contents of the output latch are output.
After reset, the output latch becomes 0, so when the port is set to output mode, a low level (same level as the start bit) is output.

This status continues until the output latch is set to 1.
If this period is longer than 1/2 the bit period determined by the baud rate, this status is considered as the start bit and the phenomenon described in your inquiry occurs.
The initialization procedure consists of setting the P71 output latch to 1, and then setting PM71 to the output port, in this order.

The following passage is included in the description of transfer using the asynchronous serial interface of the uPD784218.

Caution : In the case of UART transmission, follow the procedure below when performing transmission for the first time. (1) Set the port to the input mode (PM21 = 1 or PM71 = 1), and write 0 to the port latch. (2) Set bit 7 (TXEn) of asynchronous serial interface mode register n (ASIMn) to 1 to enable UART transmission. (3) Set the port to the output mode (PM21 = 0 or PM71 = 0). (4) Write transmit data to TXSn, and start transmission. If the port is set to the output mode first, 0 will be output from the pins, which may cause malfunction.

However, the last description
seems to contradict steps 3 and 4.

There is no problem with this procedure.
You may have misunderstood the change in status in step (2).
The detailed operation is as follows.

What setting should I perform to use 8-bit timer 2 with the clock selection method of serial interface control register 0 of the uPD78054 ? No clock is generated from SCK0 even when I set CSIM0 to 9AH.

No clock will be output from SCK0 by simply setting CSIM0.
The following initial settings are required.

When transmit data is written to SIO0, or in the case of reception, FFH is written to SIO0 in this status, communication should start and SCK0 should be output.

In the uPD780022, when ISRM0 of UART0 is set to 1 so that no receive interrupt request is generated upon occurrence of an error, are INTSER0 interrupts possible?

Yes, INTSER0 interrupts are possible.
ISRM0 is simply a function to control the generation of receive end interrupts upon occurrence of an error.
It has no effect on INTSER0.

If I wait for the time corresponding to (clock pulse width per bit x 8 bits), is this considered the end of transfer and can the next data be written?

No.
Write the next data after waiting for the transfer end flag.
Since the CPU operation and SIO operation are asynchronous, the transmission does not start immediately, even if data is written to SIO.
In order to achieve synchronization, transmission starts after a lapse of time corresponding to approximately 1.5 serial clocks (worst case) (in the case of operation using the internal clock).

In the uPD780024, I want to use SIO31 in 2-wire serial transmission-only mode, and set the SI31 pin as an output port.
Is it OK to simply set PM34 = 0 in the SIO31 transmission mode?

Yes.
Since there is no transmission-only mode for the SIO31, the SI31 pin can be used as an output port by simply setting SIO31 to the transmission/reception mode and setting PM34 = 0 (setting port 34 to the output mode).
Since SIO31 receives meaningless data during the transmission, please ignore the received data.

In the uPD784218, during use of SIO2 with the internal clock and use as UART, can I use pin 39 (ASCK2) as an I/O port?

Yes.
When using the internal clock for the serial clock, ASCK2 (pin 39) can be used as a port.

In the uPD784935, when PMC1 is set to 00011000b and the RXD2 input mode and TXD2 output mode are set, do P13 and P14 have to be set to input as the PM1 setting?

No, this is not necessary.
As described in Figure 6-10 and Figure 6-11 in the User's Manual, when PMC13 and PMC14 are set to 1 in the PMC setting, P13 functions as RxD2 input and P14 functions as TxD2 output.

When using the SIO1 automatic transmit/receive function of the uPD780232 with an external clock, is the interval time 2/fsck similarly to the internal clock?

Yes, it is 2/fsck similarly to when the internal clock is used.

With the uPD78083's UART, there is a variation ranging from 0 to several hundred μs from when data is written to transmit shift register TXS to when data transmission actually starts.
How can I get rid of this variation?

This variation occurs because the UART's baud rate clock and the CPU clock are asynchronous.
To avoid this, it is necessary to synchronize the baud rate clock with the CPU operation.
One way to reduce variation is to set TXE of ASIM to 0 when not transmitting, and set TXE prior the start of transmission.
Note, however, that this operation is not guaranteed.

Since the baud rate is determined by division of the internal clock, the actual baud rate varies slightly from the nominal value of the baud rate.
For example, when inputting a 16MHz or 32MHz clock, there is a difference of 0.16%. (Nominal value: 9600bps; Actual value: 9615bps)
Is this level of difference between the actual and nominal baud rates a problem?

In normal cases, this variation should not be a problem.
For normal UART, the margin is approximately 45% of the bit length.
When this is divided by the total bit length, the figure is a little under 4%, and even if the transmitting side and the receiving side consume half of this figure,
it is a little under 2%. Thus 0.16% is not at all a problem.

During asynchronous serial communication, what can the deviation of the baud rate for signals sent from the other party be?

The following answer covers UART0 of the 78K/0 and 78K/4.
While the allowable deviation depends on the data configuration (data length, parity or no parity), and the baud rate generator setting, a relative error of approximately 4.5% (8 bits + parity, k = 0) to 5.9% (7 bits, no parity, k = 14) should be no problem.

The concrete allowable error is expressed as


This value is the relative difference between the transmitting and receiving sides.
If there is a baud rate error arising from the operating clock of the microcontroller, the value corresponds to that baud rate error.