The ROM correction function provides a means to correct a program previously written to ROM
in a microcontroller by applying a patch to the program.
Although this function is convenient in that it can be used to correct programs already written to ROM,
it cannot be used under all conditions.
Before using this function, part of the target processing must already be included in the program to be corrected,
and external memory is required to read the corrected program.
ROM correction operations and their requirements are described below.
[1] Basic operations for ROM correction
First of all, for ROM correction to work, there must be a way to distinguish between parts of the target program
that are automatically executed by hardware (the CPU, etc.) and parts that must rely on support from the application.
The following is an example of ROM correction operations that occur once the required settings have been entered.
Outline of ROM correction processing in 78K0 device
| (1) |
When the CPU fetches an instruction during execution of a program, the target address
for fetching is compared with the ROM correction address set in the CORADn register, and if
the two addresses match, a branch instruction (BR !0F7FDH) is executed instead of the original instruction.
When this branch instruction is executed, the processing up to that point is stopped and processing branches
to address 0F7FDH.
At that time, the correction address where the match occurred is indicated by setting
the corresponding bits (CORST0 and CORST1) in the CORCN register. |
The processing described above is performed by the ROM correction hardware,
and the processing described below is performed by application programs.
| (2) |
Since the BR ! 0F7FDH instruction sets a branch at the end of the internal expansion RAM area,
it is necessary to branch the processing to the address where ROM correction processing will be
actually performed. |
| (3) |
Up to two locations can be specified for ROM correction.
The CORST0 and CORST1 bits are used to determine which addresses are being compared as matching,
and then the corresponding program (batch processing) is executed.
Be sure to clear these corresponding CORST bits at this time. |
| (4) |
Once the batch processing has been completed, processing branches back to the original program. |
As noted above, ROM correction hardware is used along with the processing program that has already been included
in the application program to execute the correction program through patch processing.
[2] Hardware preparation for ROM correction
To execute ROM correction, there must be hardware that can read the correction program.
Connect an EEPROM that is controlled by a serial interface and write the correction program into it.
In such cases, the ROM correction program must be read via the serial interface and written to internal
expansion RAM during initialization processing.
[3] Support from initialization program
In addition to preparing the hardware to be used for ROM correction as described above, certain required settings
must be provided in the initialization program.
Initialization processing for ROM correction
The processing shown in the flowchart above is required as part of the initialization processing to enable use of
the ROM correction function.
The following description refers to this flowchart.
To enable use of external memory, the serial interface must first be initialized.
| (1) |
Either set up an input port or set up a flag that indicates whether or not a particular address in external
memory must be used for ROM correction, and check this setting before starting initialization processing.
If the ROM correction function does not need to be used, skip steps (2) to (4) below and continue with the subsequent processing. |
| (2) |
Set parameters
Read the parameters (correction addresses) required for ROM correction from external memory and set them to the CORAD register. |
| (3) |
Load correction program
Next load the program to be executed for ROM correction from external memory, and write the program to the internal expansion
RAM area that will be used for actual execution of the program.
Since the internal expansion RAM will actually be used to execute the program, several dozen bytes of space must be reserved
at the end of the internal expansion RAM area for ROM correction.
These actions may be performed about the same time as when setting the parameters in step (2) above. |
| (4) |
Set COREN bits
Finally, to enable ROM correction processing, set the COREN0 and COREN1 bits (to 1) in the CORCN register
that corresponds to the ROM correction addresses to be used.
The following shows a sample program that contains the processing described in steps (2) to (4) above.
In this sample program, the subroutine GET1CH is executed to read one byte from the serial interface, and the result is entered
in the A register (the HL register is not affected).
The start address of the internal expansion RAM to be used for ROM correction is defined as PATCH.
However, ROM correction should use an area of 256 bytes or less in the internal expansion RAM.
;
; Starts initialization for ROM correction
;
MOV CORCN,#0 ; Prohibits ROM correction
MOVW HL,#PATCH ; Sets copy destination address
LOOP1:
CALL !GET1CH ; Reads one byte
MOV [HL],A ; Writes to internal expansion RAM
INC L ; Updates address
BNZ $LOOP1 ; Loops until completed to 0F7FFH
MOVW AX,!PATCH ; Reads address setting for channel 0
MOVW CORAD0,AX ; Sets address
PUSH AX ; Saves channel 0 address
MOVW AX,!PATCH+2 ; Reads address setting for channel 1
MOVW CORAD1,AX ; Sets address
OR A,X ; Checks addresses
BZ $NEXT1 ; Ignores address if value is 0000
SET1 COREN1 ; Sets channel 1 as valid
NEXT1:
POP AX ; Recovers channel 0 address
OR A,X
BZ $NEXT2 ; Ignores address if value is 0000
SET1 COREN0 ; Sets channel 0 as valid
NEXT2:
;
; Ends initialization for ROM correction
;
|
|
[4] Pre-processing for ROM correction
When the addresses match, the BR !0F7FDH instruction is executed instead of the instruction
to be corrected and the processing branches to address 0F7FDH.
Since instructions are set only as far as address 0F7FDH, so a branch instruction is set here
so as to branch the processing to the start of the processing that executes the actual ROM correction.
[5] Configuration of programs for ROM correction
The correction programs and parameters used for ROM correction are described below.
Two addresses for setting ROM correction, the correction program, and a branch instruction for entries
must be prepared in the external memory.
For simplicity's sake, a 64-byte area is reserved as the target area.
The 64 bytes of data for this area are transferred to the end of the internal expansion RAM area (0F7C0H to 0F7FFH).
The following program should be then set up, with RETADR0 as PATCH0's branch address for ROM correction's first target
address and RETRAD1 as PATCH1's branch address for ROM correction's second target address.
Define PATCH0 for ADDR0 and PATCH1 for ADDR1 by a DW pseudo instruction.
In the initialization processing for ROM correction, the contents of ADDR0 and ADDR1 are checked.
If they are "0000", then ROM correction is not used in the corresponding channel.
If they are not "0000", ROM correction is used in the corresponding channel
(the corresponding bits in the CORCN register are set to 1).
PATCH CSEG AT 0F7C0H
ADDR0: DW PATCH0 ; Address where correction will be set
ADDR1: DW PATCH1 ; Address where correction will be set
STARTADR:
BT CORCN.0, $PROCE0
PROCE1:
CLR1 CORCN.2 ; Processing corresponding to CONST1
; ; Required processing is described here
; ; Required processing is described here
BR !RETADR1 ; Branch to main routine upon completion of processing
PROCE0:
CLR1 CORCN.0 ; Processing corresponding to CONST0
; ; Required processing is described here
; ; Required processing is described here
BR !RETADR0 ; Branch to main routine upon completion of processing
ENTRY CSEG AT 0F7FDH
BR !STARTADR
END
|
[6] ROM correction conflicts
It is quite unusual for multiple ROM correction processes to occur at the same time.
However, when ROM correction has been set up as an interrupt service and an interrupt occurs during ROM correction processing,
it is possible that other ROM correction processing may be executed while the interrupt is being serviced.
In such cases, priority among ROM correction channels can be set by checking the CORST bit value in the highest-priority
channel of the program targeted for ROM correction.
Once the processing has been prioritized in this way, ROM correction processing can be performed even when an interrupt has occurred.
SITE MAP
