Reset

In the uPD78P014, what is the port status when the reset signal is input in the oscillation stopped status?

When a normal reset signal is input, the port enters the input mode.

What is the port status when oscillation was stopped from the beginning when the power was applied?
(Reset signal is input.)

The port enters the input mode.
78K0 Series products acknowledge resets without any clock input.
Once reset is acknowledged, the clock oscillation stops.

How is reset processing execution (jump to startup routine) performed in the middle of a program?

The simplest method is to use a watchdog timer timeout.
In all other cases, to perform processing by software only, a program must be written using the assembler.

[Caution]
In some cases, simply branching to the reset vector cannot realize the same state as reset.

When the power supply rises slowly (approx. 50ms), the CPU does not always work.

This is probably due to the fact that the reset time is abnormally short compared to the stabilization time for the supply voltage.
When the reset pulse width is shorter than the power supply rise time, reset release occurs during the interval in which the power supply has not yet reached its normal level.
Abnormal operation occurs due to the fact that the supply voltage is lower than the operating voltage.

Please select a time constant that enables reset to be maintained during the time in which the supply voltage stabilizes.

Is it OK if the interval during which the reset signal is input lasts several seconds?

Yes, there is no problem to input the reset signal for a long time.
While there is a restriction as to how short the reset signal can be, there is no such restriction about how long it can be.

I am using several CPUs, and I want one of these CPUs to initially stop operating for a given time, so I am thinking to apply a continuous reset to that CPU.
Are there any problems with this method?

While the reset signal is being applied, almost all the pins are high impedance.
In this status, when the pin potential becomes an intermediate level, a through current passes through the input ports.
Although the through current that passes through each input pin may be small, it can be a large cumulative current that passes through all the pins.
Please implement countermeasures such as pulling up externally via a resistor so that an intermediate level does not occur in any of the pins.

The LEDs connected to the ports light upon reset. What is the cause and how can I prevent it?

At reset, all the ports enter the input mode (high-impedance status).
When TTL is used for the external buffer, there is a high likelihood that the high-impedance status will be judged as a high level.
If the circuit is designed so that LEDs light when the port outputs are high level, the LEDs will light as a result.

The handling to prevent this is to make the LEDs light when a low level is output.

When the CPU is reset, is the internal RAM data held?

RAM data hold is not guaranteed in the case of reset during normal operation.
Since reset is applied asynchronously to normal operation, a reset may be applied while writing to RAM is in progress.

In this case, writing to RAM may not be performed normally.
Therefore, the RAM data cannot be guaranteed if a reset is applied during normal operation.
This is a problem of the timing at which reset is applied.

No problem occurs when a reset is applied while RAM is not being written.
However, if a reset is applied while RAM is being written, the width of the reset signal becomes smaller than the specified value, and the address may change while the write signal is on, resulting in data being written not only to the address that was being written, but also possibly to other addresses.

The reset signal and unmasked interrupts are given as the triggers for releasing the STOP mode in the uPD78F9116A.
But since oscillation is stopped in the STOP mode, does this prevent a reset from being applied?

Since reset can be acknowledged even when there is no clock, the reset signal can be used to release the STOP mode.
Since the delay time of the reset signal depends on the analog delay, it can be used without problem.