PWM

Regarding the PWM output cycle and pulse width of the uPD780308, could you describe the basic items using the following example?

Conditions	- Main system clock frequency: 5.0MHz - 16-bit timer counter clock: 5.0MHz   (settings of MCS=1, TCL06=0, TCL05=1, TCL04=0) - 16-bit capture/compare register CR00=N
PWM output	- Count clock: 1/(5MHz) = 0.2μs - Cycle: 0.2μs x 216 = 13.1ms - Pulse width: 0.2μs x (N + 1)

The specified duty is not output continuously in 1 cycle with this configuration.
The PWM output in question is configured to obtain a 14-bit resolution using 64 pulses.
The higher 14 bits of CR00 specify the total active time (sub-cycle).

This sub-cycle consists of 64 basic pulses. There are two types of basic pulses, "n" basic A pulses and "m" basic B pulses, and a total of 64 basic pulses is used. (A and B are explained below.)

If one sub-cycle includes n x A, then it includes m x B (= 64 - n).
m + n = 64
The number n is specified by the lower 6 bits of the 14 bits.

One basic pulse cycle (basic cycle A and basic cycle B) is specified by the higher 8 bits (256 clocks) of CR00.
In this example, the basic cycle is 51.2μs.

Therefore, in the example you inquire about:
Sub-cycle = basic cycle (51.2μs) x 64 -> 3276.8μs

The waveform actually output is a waveform made up of a balanced mix of A and B.
However, the total included in the sub-cycle is the above-described number.


The difference between A (attribute) and B (basic) is as follows.

The basic pulse duty is specified by the higher 8 bits of CR00, and the waveform specified by the higher 8 bits is basic B.
Basic A is a pulse that has a duty of one more clock than B.
In other words, it is a pulse one unit higher than the value specified by the higher 8 bits.

If the middle 6 bits of CR00 are 0, the sub-cycle consists entirely of basic B.
If the value of the middle 6 bits is 1, it consists of 1 basic A and 63 basic B; if the value of the middle 6 bits is 63 (all 1), it consists of 63 basic A and 1 basic B.

The basic cycle (period of 256 clocks) is determined by the higher 8 bits of CR00, but this yields an accuracy of only 8 bits.
By mixing the specified number of basic A indicated by the middle 6 bits, 14-bit PWM resolution is achieved.

(Supplement)
By splitting the pulse in this way, the number of pulses in the entire (3276.8μs) period can be increased.
In other words, the PWM output waveform frequency element can be increased.
A low-pass filter is provided for this pin, but a higher frequency can shorten the filter time constant.
This design allows the use of a part (capacitor) that is smaller to this extent.

Regarding the uPD784038, in section 13.2.3 PWM modulo register (PWM0, PWM1), can 00h be used as the setting value for PWMn when PWM is not used?

The modulo register setting is not required if output is disabled using the PWMC register.
However, if you want to set this register, 0FFF0H is recommended.

In the uPD789177, there are cases when I want to make PWM output 0.
In this case, it looks as if this could be done by setting CR8n to 00H, but p.152 of the User's Manual (U14186E 2nd edition) says the following:
What should I do if I want to use PWM output at low level (as PWM 0%)?

Reset TOE8n and set it to the port mode.
If CR8n is set to 1, TOE8n can be controlled at the INTTN8n timing with the F/F in the low status.

What does "PWM may not be output normally" mean?

The meaning can be understood by looking at the timing chart on same page.
The reason why PWM may not be output is that the state of the output F/F cannot be defined since the valid timing of the signal setting the output F/F (output at count 00) and the signal resetting the output F/F (output following a match with CR8n) will occur at the same time.