Power Supply

In the uPD780054, if analog and digital power supplies and grounds are connected to each other, is it impossible to obtain ADC characteristics?

When sharing the same power supply for the analog and digital circuits, influence is received from the digital side.
Therefore, be sure to use separate power supplies for the analog and digital circuits (but with the same potential).

Is it OK to use two power supplies, VDD (5 V ± 10%) and AVDD, AVREF (5V ± 2%) for the uPD780024A ?
In this case, I will use a Schottky diode so that VDD+0.3V is not exceeded.

Yes, such an approach would not cause a problem.
When VDD becomes low, the effect of VDD variation may be transmitted to AVDD or AVREF via the Schottky diode, so design VDD a little bit higher than AVDD so that no current passes through the diode.

In the uPD78083, what is the minimum operation guaranteed voltage and data hold voltage?

The minimum operation guaranteed voltage differs depending on the operation mode.

The minimum operation voltage is as follows under various conditions.

Condition		Cycle Time	Guaranteed voltage(MIN)
When using A/D		-	2.7V
When not using A/D	Internal clock is same as oscillation clock	0.8μS	2.7V
		0.4μS	3.5V
	Internal clock is 1/2 of oscillation clock	2.0μS	1.8V
		0.8μS	2.7V

Data hold is guaranteed up to 1.8V in STOP mode.
The conditions for data hold are described in the data sheet.

In the uPD78F0034A, is only VDD1 required for backing up the power supply?

No, power supply backup is not possible just with VDD1.
AVDD, VDD0 and VDD1 must be made the same voltage.
Different pins are used only for noise reduction purposes, in which case they are connected internally by a parasitic circuit.
When AVDD, VDD0 and VDD1 are not the same voltage, the current may leak through this parasitic circuit.

The uPD78F0058 has 4 power supplies (VDD, VDD0, AVref0, AVref1).
Are they connected inside the microcontroller?

VDD0 and VDD1 are internally connected via a parasitic circuit.
Consider AVref1 to also be internally connected.
Note that this connection is done via a parasitic circuit and is not a regular connection; therefore external connection is required.

What is the VDD operating voltage range (temperature range of -40 to +85°C) when using the uPD780058 Series at 5MHz (0.4μs)?

The operating power supply voltage range with a 0.4μs cycle time is 3.5V to 5.5V in the uPD780058.
The product specifications are described in the data sheet. Please refer to the data sheet.

In the uPD78F0058, when the reset pin is fixed to low level, is the current that flows to VDD equivalent to the current during low-current-consumption operation in the STOP mode?

No, the current at reset is not the same as that in the STOP mode.
Since the current varies according to the pin status at reset, the same current as that in STOP mode cannot be guaranteed.
When a reset is applied, the ports used as outputs also become input ports.
Therefore, in some cases, the same status as when the pins are open occurs during input.
At this time, a through current flows, and the current can be expected to increase when the STOP mode is entered.

In the uPD784216, to what extent does the power consumption fall in the HALT mode, STOP mode, IDLE mode, low-power-consumption mode, low-power-consumption HALT mode, and low-power-consumption IDLE mode?

The operating current of the CPU itself in the various operation modes is as follows.
This current does not include the pull-up resistance and load, nor the current that flows to the A/D and D/A converters.

Assuming that what you refer to as the low-consumption mode means the current during subsystem clock operation, the reduced values are as follows.

For details, refer to the data sheet.

The uPD789012 power supply voltage specification is 1.8V to 5.5V, but what are the specifications of the variation rate when there is a variation?

Although no specifications have been established regarding the above, users are requested to observe the following conditions.
Consider the two above points as guides.
Also, there are operating frequency restrictions based on the supply voltage.
Strictly observe the supply voltage conditions for the operating frequency.

In the uPD789025, when the power supply of the CPU is off, is it a problem if a voltage is applied externally to a given port?

This usage is not allowed.
A voltage exceeding VDD+0.3V cannot be applied to the ports of the uPD789025.
If this is not observed, it represents a violation of the absolute maximum ratings, and the device may be damaged as a result.
Latch-up damage in particular may occur when the power supply of the uPD789025 is applied.

Moreover, since a protection diode is connected to VDD from each port, in the status described in your inquiry, a current flows to VDD (in this case, ground potential) via the port, so be sure to refrain from this kind of usage.

In the uPD789417, VDD0 is the power supply for ports, and VDD1 is the power supply for other than ports.
Is it possible to supply a different supply voltage for each?

It is not possible to supply different voltages to VDD0 and VDD1.
Please supply the same voltage to VDD0 and VDD1.
The reason for the separate power supply pins is a countermeasure to avoid the influence of digital noise on the analog circuit.

Is the "VDD" listed for the high-level input voltage/low-level input voltage in the DC characteristics table on p.37 of the uPD789407A Data Sheet (Document No. U14024) "VDD0" or "VDD1" ?

They are both the same.
The same voltage must be applied to VDD0 and VDD1.
(The reason separate pins are employed is to strengthen the power supply line.)
VDD1 could even be referred to as the port block power supply VDD0.