Memory

What are the basics about external expansion of memory?

Some microcontrollers have a memory expansion function in addition to their internal ROM or RAM.
The following figure shows the relationship between the internal and external addresses.
Depending on the device and/or settings, only part of the address information is output externally.


The following describes a case where the CPU handles a 16-bit address space and the internal ROM consists of 24KB, as shown in the CPU memory map above.
In this case, the addresses from 6000H can be used as the external expansion area.
For simplification purposes, the external expansion area is the 32KB area from 6000H to DFFFH.

(1) Case when 12-bit address output is specified (4 KB expansion)
In this case, the memory that can be expanded physically is 2¹² = 4KB.
When the CPU accesses the address 6000H, the address 000H corresponding to the lower 12 bits of 6000H is output.
When 7000H or 8000H, 9000H are accessed, the lower 12 bits similarly become 000H.
This means that same physical address is accessed and the image of same address appears every 4KB.

Memory map during 4KB expansion :


(2) When 14-bit address output (16 KB expansion) is specified
In this case, the memory that can be physically expanded is 2¹⁴ = 16KB.
When the CPU accesses the address 6000H, the address 2000H corresponding to the lower 14 bits is output.
Similarly, 3000H is output at 7000H, 0000H at 8000H, 1000H at 9000H, 2000H at A000H, and 3000H at B000H.
Therefore, in the case of use from 6000H, the relationship between internal addresses and the row of external addresses is inverted.
This is no problem when RAM is expanded, but caution is required when connecting PROM or flash memory.

In order to avoid this, using only the addresses from 8000H is recommended.
Moreover, since the same external address is output at multiple addresses, when RAM has been expanded, it is necessary to manage so that the same physical address is not accessed via different logical addresses.

Memory map during 16KB expansion :


(3) When 16-bit address output (64 KB expansion) is specified
In this case, a 64 KB space can be used externally.
However, since the CPU itself can handle only a 64 KB space, the memory that can be expanded externally is only the area corresponding to 64 KB minus the internal memory capacity of the CPU (depending on the device, the memory that can be externally expanded may be even smaller).
At this time, the external addresses and internal addresses are the same value.
Therefore, the part that overlaps the internal ROM (in this case, 0 to 5FFFH) may be wasted.

Memory map during 64KB expansion :


Related FAQ :
How can I allocate variables and code to other than normal memory?

In the external memory access timing chart of the uPD780031A (Document No. U14044), RD and WR are shown as becoming active one after the other.
Does this signify that read-modify-write access is performed both for read access and write access?

No.
As described in Figure 20-5 (External Memory Read Timing) in CHAPTER 20 (EXTERNAL DEVICE EXPANSION FUNCTION) in the User's Manual, the data write part does not occur when the external memory is read; similarly, a read operation does not occur when the external memory is written, as described in Figure 20-6 (External Memory Write Timing).
However, time corresponding to this read operation is required. (Assume that the signal becomes active during the interval required for read-modify-write.)

What is the method to connect SRAM, etc., to the uPD780078?

Regarding the circuit, see the circuit below. The capacity of the external SRAM is 32KB, but the attached circuit is an example for the 4KB expansion mode.
To use a larger memory capacity, either use the 16KB mode or the 64KB mode.
If wishing to secure the largest capacity of internal ROM, use the 4KB mode, and connect the output port to A12 to A14 of the SRAM (bank switch).

With regard to the timing of read operations, data is output from the SRAM while addresses are continuing to be output on the data bus, so data conflict may occur temporarily.
One possible countermeasure is to delay the falling edge of the OE signal for the SRAM.
If this countermeasure is taken, the read timing may be too short, so insert a wait cycle via a register setting.

Also, the timing differs depending on the supply voltage and clock speed, so revise the timing according to the actual usage conditions.


When not using A12 to A14 of SRAM, connect them to GND.
If you wish to use A12 to A14, connect them to the addresses of the microcontroller or to output ports.

What is the actual voltage at which the RAM values of the uPD780308Y become undefined?

The actual voltage value is not known.
The guaranteed value for the data hold voltage is not the operating supply voltage but is listed in the data sheet as a separate item, and the minimum value is 1.6V.

Is program execution possible using internal high-speed RAM?

No, it is not.
Fetching from internal high-speed RAM is not possible.

I have problems with external memory access in the uPD78P4038.
What is the access method?
In the 78K/2 Series, for example, external access is possible using "MOV A, &xxxxh", but what is the access method for the 78K/4 Series?
(By the way, the 4KB expansion mode is used.)

Please access addresses where no internal memory is mapped.
In the 78K/4, there is no special addressing mode for external access.
If memory areas other than internal ROM, RAM, and SFR are accessed, it is external access.

Concretely, in the case of the uPD78P4038 you inquire about, the internal PROM covers a 128KB area from 0 to 1FFFFH.
So when the addresses from 20000 to FEDFF are accessed (when the LOCATION 0FH instruction is executed), external memory is accessed.
Since access is performed in the 4KB expansion mode, when an address from address 20000 to FEDFF is specified (when the LOCATION 0FH instruction is executed), the same address is accessed every 4KB (because only the lower 12 bits of the address are output, and the higher bits are not output).

I have a question about the data read timing of the uPD784038.
What is the timing when the CPU reads data that has been placed in external memory using the local bus interface function?
Is it all right to assume that it is the "last clock edge of the period during which RD* = L" ?

No, the clock that is used internally cannot be seen from the outside.
Therefore, thinking in terms of timing in relation to the clock is meaningless.
The clock that is output as the CLKOUT signal is a different clock from the clock in the CPU.
Since CLKOUT is a signal for operating external circuits, the phase relationship with the clock used to operate the CPU cannot be specified.
As mentioned above, the falling/rising edge timing of the clock in the CPU cannot be known from outside.

What is the value of the internal EEPROM of the uPD78E9860 in the default status?

The value of the EEPROM is "00" as a factory-set condition for shipment.
This is not a value guaranteed for the device but is the value at present.
Note that it may be changed because of production modification.

Data cannot be correctly written to the internal EEPROM (0xF800 to 0xF81F) area of the uPD789860. What should be done?

The procedure of writing data on RAM to the EEPROM is shown below (in the following example, the INTEE0 interrupt is not used and, instead, polling of a flag (EWST10) is used).

(1) Set the write timer and ERE10 bit (starting operation of the EEPROM) by setting the EEWC10 register.
(2) Set the EWE10 bit of the EEWC10 register (setting the write mode).
(3) Wait for 1 ms or more (until writing is enabled).
(4) Write 1 byte (as a result, EWST10 is set to 1).
(5) Wait until EWST10 is cleared to 0 (until writing of 1 byte has been completed).
(6) Proceed to the next address of the data to be written.

Repeat (4) to (6) as many times as the necessary number of bytes.

(7) Clear EWE10 (exit from the write mode).

An example of a writing program in which the above processing is described in an assembly language is shown below.
This is an example of writing.

This program example is a subroutine that sets to HL the EEPROM address to which data is written, and the address of data to be written, to DE.
The number of data to be written has been already set to B.
As necessary, read the written data for checking.

;
;   Write EEPROM 
;   Input parameter 
;   HL  Data Pointer for EEPROM 
;   DE  Data Pointer for Read 
;   B   Data number 
;    
    
WRITE: MOV  A,#4CH  
       MOV  EEWC10,A       ; Set ERE10 & Set Timer to 3.71mS 
       SET1 EWE10          ; Set EWE10 
       PUSH DE  
       MOVW DE,#279        ; 1mS 
LOOP2: DECW DE  
       MOV  A,D  
       OR   A,E  
       BNZ  $LOOP2  
       POP  DE  
LOOP3: MOV  A,[DE]         ; Read Data 
       MOV  [HL],A         ; Write Data to EEPROM 
       INCW HL  
       INCW DE  
LOOP4: BT   EWST10,$LOOP4
       DBNZ B,$LOOP3  
       CLR1 EWE10          ; Write end 
       RET

The concept of this program also applies to the uPD789862 subseries.