LCD

0001: Method of LCD drive voltage generation, and connection

The LCD controller/driver in the 78K0 and 78K0S Series can be classified by the method of LCD drive voltage generation.
The latest devices adopt an internal booster method instead of the conventional resistor split method for generating the LCD drive voltage.

1. Summary of drive voltage generation

(1) Resistor Split
This method was adopted in previous MCUs due to its simplicity.
With this method, a dividing resistor generates the required voltage.
Except for the mask versions, the resistor is not necessarily built in the device, and may be external.
The voltage changes to 1/3 bias or 1/2 bias in accordance with the display system by external short-circuiting (there are some devices in which the voltage is fixed).
Although the LCD drive voltage is usually lower than the power supply voltage, there are some devices that enable input of an LCD drive voltage that is higher than the power supply voltage, such as the uPD789327 Subseries.
(2) Capacitor Split With this method, a dividing capacitor generates the required voltage instead of a dividing resistor.
Unlike the resistor split method, current does not constantly flow, so the power consumption is reducible.
This method also divides the voltage, so the LCD drive voltage will also be lowered during low-voltage operation.

(3) Booster type
The voltage is boosted and the LCD drive voltage is generated from the reference voltage by connecting an external capacitor.
Usually, while a capacitor is connected between the CAPx pins, a capacitor is also connected between the VLCx pin and VSS.
This method enables generation of an LCD drive voltage of 3V or 4.5V even when VDD is low.
Moreover, since a resistor is not used and the operating current is small, it is suitable for battery operation.
This method is being increasingly used in new devices.


Table of LCD drive voltage generation of each subseries

Subseries	Drive voltage generation	Usage
uPD780308	Resistor Split	Fig.1
uPD780318 uPD780328 uPD780338	Booster type	Fig.6
uPD780958	Capacitor Split	Fig.5
uPD780344 uPD780354	Booster type	Fig.7
uPD789306 uPD789316	Booster type
uPD789327	Resistor Split	Fig.2
uPD789407A uPD789417A	Resistor Split	Fig.3
uPD789426 uPD789436 uPD789446 uPD789456	Booster type	Fig.7
uPD789467	Booster type
uPD789478	Resistor Split	Fig.4
uPD789488	Booster type	Fig.7
uPD789830	Resistor Split	-
uPD789835	Booster type	Fig.8

Fig.1 Resistor Split 1 : Example of Main Connections (uPD780308 Subseries)
(with LEPS=0, logical-inference-per-second=1)



Fig.2 Resistor Split 2 : Example of Connection (uPD789327 Subseries)


Fig.3 Resistor Split 2 : Example of Connection (uPD789407 / 9417 Subseries)


Fig.4 Resistor Split 2 : Example of Connection (uPD789478 Subseries)


Fig.5 Capacitor Split : Example of Connection (uPD780958 Subseries)


Fig.6 Booster type 1 : Example of Connection (uPD780318 / 0328 / 0338 Subseries)


Fig.7 Booster type 2 : Example of Connection
(uPD780344/345, uPD789306/9316, uPD789426 to uPD78946, uPD789467, uPD789488 Subseries)


Fig.8 Booster type 3 : Example of Connection (uPD789835 Subseries)

VLCD can be varied from 4.0V to 5.5V by setting the LCD boost voltage level setting register (VLCD00)

Is the LCD voltage of the uPD789304 only VDD x 1 or VDD x 1.5?
Can't it be used two ways, as follows?
1/3 bias, VDD = 5V, VLCD = 3V
1/3 bias, VDD = 3V, VLCD = 3V

Yes, this is possible.
If the LCDVA0 register is set to 1, a supply voltage of 3V can be obtained within the VDD range of 1.8V to 5.5V.
The LCD drive voltage controller obtains 1V or 1.5V from VDD via a regulator, and generates a voltage for the LCD that is two and three times 1V or 1.5V.
The regulated voltage can be set to 1.0V or 1.5V using the LCDVA0 register.
This voltage is charged into a capacitor between the CAPH pin and the CAPL pin, and the same voltage is obtained between VCL2 and GND, double this voltage is obtained between VLC1 and GND, and triple this voltage is obtained between VCL0 and GND.

In the uPD789405A, I am using LCD dividing resistors of 10kΩ each. Is this OK?

It depends on the LCD panel and wiring that are used.
In the case of 10kΩ, there should be no problem.

Please tell me more about the VAON0 setting in the LCDM0 register of the uPD789407.

When using the LCD on a low supply voltage, set VAON0 to 1.
If low voltage operation is not required or if operation of the LCD on a low voltage is not recommended, set VAON0 to 0.
Please refer to the LCD Characteristics Mode specifications table in the Data Sheet.
For reference, the settings are as follows.
Low voltage mode (VAON0 = 1) 2.2V min.
Normal mode (VAON0 = 0) 2.7V min. (1/3 bias)
Normal mode (VAON0 = 0) 3.0V min. (1/2 bias)

What is the recommended external circuit for connecting an LCD to the uPD789446?

Four capacitors (0.47μF each) are required. Connection should be as follows.

Between CAPH pin and CAPL pin: 0.47μF (C1)
Between VLC0 pin and GND pin: 0.47μF (C2)
Between VLC1 pin and GND: 0.47μF (C3)
Between VLC2 pin and GND: 0.47μF (C4)

The capacitor between the VLCn and GND can be an electrolytic type, but please select a capacitor with a small leakage.
The capacitor between CAPH and CAPL must be a non-polar capacitor.

The connection of the LCD panel and microcontroller (COM0 to COM3, S0 to S14) is as described in Figure 13-12 of the User's Manual.