I2C Bus

Introduction
The I²C bus is a serial bus proposed by Philips. It supports data transfers among multiple devices using just two signals.
(Payments for licenses and royalties have not been required since the Philips patent lapsed in August 2004.)

What are the main specifications for the I²C bus?

The I²C bus uses two signals, a serial clock signal and a serial data signal, to transfer data among multiple devices.

• Standard mode:	up to 100 Kbps
• Fast mode:	up to 400 Kbps
• High-speed mode:	up to 3.4 Mbps

A device that supports one of the faster transfer rates must also be able to operate when connected to a bus with a slower transfer rate.

A bridge must be used to separate a high-speed mode bus from a standard mode or fast mode bus.
Although communications are synchronized with a serial clock signal, it is still possible to use just one bus to connect several devices (called "masters") that control communications via with a specified communications partner (this is called a "multi-master" system).
Consequently, the protocol not only determines how data is handled but also specifies destination addresses and bus arbitration data.

(1) Connected devices

Devices that can be connected to an I²C bus are classified as follows.

• Master only:	Microcontrollers are mainly used as masters.
• Slave only:	EEPROMs, A/D converters, D/A converters, etc.
• Master/slave (shared):	For when both master and slave functions are used in a multi-master system

Master-only functions are often used with microcontrollers, such as when connecting to an EEPROM. Slave functions are also used for some applications.

(2) Interface signal

An interface signal is normally driven via open drain output in order to connect output from multiple devices.
The low-level interface signal is output from a device and the high-level interface signal is provided via a pull-up resistor.
When using high-speed mode, a current source pull-up is included in each device to accelerate the signal's rise time.

Unless otherwise specified, the following descriptions pertain only to the standard bus and fast bus.

Two voltage levels are specified for the bus signals.
Since recent microcontroller models enable the power supply to be modified, the pull-up resistor for the I²C bus is connected to VDD, so that the high-level input voltage becomes 0.7VDD (min).
Older devices or other devices with fixed power supply voltages are connected to a 5 V ± 5 % voltage, which means that the high-level input voltage becomes 3 V (min).

(a) Serial clock (SCL)
Communications are synchronized with this SCL clock signal.
Normally, during communications SCL is output by a master device, and the transmitting device modifies the serial data when SCL is low and retains the data when SCL is high.
However, if the slave device has not been set up for communications, standby is set by setting SCL to the low level, until the data can be synchronized.



(b) Serial data (SDA)
This signal is used to transfer data in synchronization with the SCL signal.
SDA signals can be transmitted from master devices and slave devices.
Acknowledge (ACK) signals for the data being transferred are also sent as SDA signals, and they are transferred in the reverse direction relative to the 8-bit data signals.
During normal communications, the SDA signal changes when SCL is low.



If the SDA signal changes when SCL is high, it becomes a control signal for start conditions, stop conditions, etc.

(3)Basic communication methods

[Start condition]
To start communications, the master must first obtain bus access.

To do this, it issues a start condition.
This condition is implemented when SDA is set to low level while SCL is at high level.

If either SDA or SCL is already at low level at that time, it means that another master is currently using the bus, so communications must be set to reserved status since no new communications can be started.

If the master device that is not able to use the bus is also able to function as a slave device, communications standby mode is set for it as a slave device.
However, if two or more masters have issued a start condition, it is not possible at this stage to set a priority among them.

In addition to being used to obtain bus access in order to start communications, the start condition is used to switch the data transmit/receive direction between the master and slave devices while the bus is still being accessed.
In such cases, the start condition is called a restart condition.
For a specific example, see [Restart condition] describing restart conditions below.

[Address and arbitration]
After the start condition is issued, 8-bit data that includes a 7-bit address specification and a one-bit transfer direction specification is issued to identify the slave device.

When two or more master devices issue the start condition, it means that each device transmits a slave address.
Since the I²C bus gives higher priority to lower values, communications that are directed to the lowest slave address take priority (i.e., the slave for which SDA is held at low level).
This principle is used to arbitrate bus access.



An ACK (low) signal is returned from the selected slave device at the ninth clock cycle of SCL in response to the transmitted address and transfer direction information.
(A wait occurs when SCL is being pulled low at this time. This wait will be described in [Wait] below.)

If the specified slave device does not exist, there is nothing to pull the bus signal to low level, so an ACK may not be returned.
If an ACK is not returned, the communications are stopped at that point; the master issues a stop condition to stop use of the bus.

[Data transfer]
Data transfer begins once communications with the slave device has been established.
At that time, during the wait status that is in effect while SCL is at low level, the slave device sets up the transfer direction according to the eighth bit of the address data (transfer direction specification bit). And when this setup is completed, SCL is no longer held low.
Now SCL can be controlled by the master device, and data transfer occurs in synchronization with SCL signals from the master device.
The timing of these operations is illustrated below.



[Acknowledge]
Data is transferred in 8-bit units, and an acknowledge (ACK) signal is returned when the transferred data has been received.
Whenever data is transmitted from a master device to a slave device, an ACK must be returned by the slave device when it receives the data.
When an ACK is not received, it informs the master device that the data was not received.

When the master device is the receiving device, if it does not return an ACK in response to the last received data, this informs the slave device that the communication session has ended.
When the slave does not receive an ACK for the final transmitted data, it concludes that the communication session has ended, at which point it stops any further transmission and sets SDA to high level.
If this processing is not performed before the slave starts transmitting the next data, SDA will be pulled low, which will prevent the master device from issuing a stop condition.

[Wait]
When the slave (or master) pulls SCL to low level, communication is stopped (set to wait mode).
Normally, a wait is set either after the eighth clock cycle (when data transfer is completed but before an ACK is returned) or after the ninth clock cycle (when an ACK has been returned but before the next transfer).

A wait is set at the eighth clock cycle when determining whether or not to return an ACK in response to data on the receiving side.
The transmitting side sets a wait after the ACK (at the ninth clock cycle).
This confirms the ACK response and determines the next operation.

[Restart condition]
In cases such as with EEPROM devices, where the device contains internal address information in addition to the device's own address, the I²C bus's address can only be used to select the device.
The address information that specifies which of the device's memory addresses to use, therefore, must be transmitted as data.
When writing, the write data can be transmitted after the memory address, as shown in the example below.
When reading the data, however, transfer direction must be switched.



A read example is shown below.
Bus access begins when the first start condition is issued, and the device's address is specified (in this time, a transmission from the master is specified).
Afterward, the device's internal address is transmitted as data.
A read operation cannot yet occur, so a second start condition is issued.
ST2 shown in the figure below is restart condition.

Later, a device is again specified by an address, but this time it specifies transmission by a slave device.
The subsequent data will be transmitted from a slave device to a master device, so a read operation is enabled.



[Stop condition]
When the data transfer is completed, the bus is released.
A stop condition is used to do this.

The master device sets SDA to low level while SCL is already at low level, then it sets SCL to high level.
After this, the stop condition is set when SDA goes to high level.

When writing to an EEPROM, the actual write operation in the device occurs once the stop condition is detected.

What are the other specifications and caution points beyond the specifications?

(1) Addresses
A 7-bit address field is used to specify the slave device's address, but not all of these bits can be used without restrictions.
For the first four bits of these address bits, the values "0000" and "1111" have restricted uses.
Any address that starts with "0000" is used as a general call address (0000 000).
Any address that starts with "1111" can specify a 10-bit slave address when the address includes one byte after the two-bit value "xx" in "1111 0xx".
However, it is unlikely that ordinary microcontrollers can use 10-bit addresses.

(2) Bus's initial status
When attempting to access the I²C bus as a master device, it is impossible to determine fully whether or not the I²C bus is being used unless it is in its initial status.
Normally, it can be assumed that the bus has been released when either SCL or SDA is being held at high level, but since there is no upper limit on SCL's high-level period, it is impossible to judge how long a wait is necessary to release the bus.
Accordingly, this must be determined by a host program rather than by a controller.

(3) Reset during operation
When a reset is issued during a communications session, ideally all bus-connected devices should be able to recognize the reset, but some devices such as EEPROMs lack this type of reset signal.

In such cases, if an EEPROM outputs a low-level signal to the SDA terminal, it is not possible to issue either a start condition or a stop condition, so the bus cannot be used. This problem cannot be resolved by a controller.

Consequently, SCL should be driven by an output port, which outputs an SCL pulse.
This enables the EEPROM to continue outputting the remaining data for 1-byte.

When the EEPROM outputs a high-level signal or when its output is completed without returning an ACK signal, the next output is stopped and SDA goes to high level.
At this point, a start condition or a stop condition can be issued, so the bus can be used.

The I²C bus of the uPD78P0308Y is an open-collector signal.
Which value should I use for the pull-up resistor for this line?

The I²C bus standard is decided by Philips.
For the detailed specifications, refer to the Philips I²C bus specification.
http://www.semiconductors.philips.com/buses/i2c/

I set STT0 and SPT0 simultaneously in the initial settings of the I²C serial bus of the uPD78F0034A, but the settings did not go well.
Could you describe the setting methods for the start condition and stop condition?

There are problems concerning basic aspects.
Setting STT0 and SPT0 simultaneously is prohibited. Avoid such a setting.
First, generate the stop condition, and then generate the start condition.
For generating the stop condition, select the clock using IICCL0 and then set the IICE0 bit and SPT0 bit of the IICC0 register.
Generation of the start condition starts after the stop condition is detected.

Please show a processing example (master operation) in the case of connection to external EEPROM via the I²C bus.

1. Outline of processing procedure
Communication process is shown below.

(0)	Set ports. (Setting of PM32, 33 to 1, and P32, 33 to 0)
(1)	Set transfer clock.
(2)	Set control register. (9-clock wait mode)
(3)	Set port. (Set PM32, 33 to 0)
(4)	Issue stop condition and check if bus is released. (Check if interrupt or SPD0 is set.)
(5)	Issue start condition and take exclusive control of bus. (Check that STD0 is set.)
(6)	Transmit slave address and check existence of the slave (ACK). (Check ACKD0 at the interrupt timing. If there is no ACK, stop transfer.)
(7)	Transmit the EEPROM address.

In the case of writing data to EEPROM, the following steps are then performed.

(8)	Send write data and check ACK using an interrupt. (If there is no ACK, end transfer operation.)
(9)	If write data remains, repeat from step (8).
(10)	Issue a stop condition to stop writing. (The EEPROM then starts writing the transmitted data to its memory block.)

In the case of reading data from EEPROM, perform the following steps.

(11)	Issue a start condition and set the data transfer direction to the read direction.
(12)	Set 8-clock wait and enable auto ACK mode.
(13)	Write dummy data (0FFH) to start transfer.
(14)	If the reception completion interrupt is generated, read the data.
(15)	Once all the data has been received, disable auto ACK mode and set 9-clock wait and release the wait at the timing of 8th clock.
(16)	Wait the interrupt at 9th clock and issue a stop condition.

2. Processing flow
The processing flow is shown in the form of a PDF file.
(Sorry, the PDF file is constructing now.)
For simplification purposes, it is assumed here that all the data can be read and written continuously.

3. Notes
(1) About ACK

Loops are prohibited during ACK wait when ACK was not received.
The ACK timing in I²C is fixed, and if ACK is not received at this timing, no ACK will be perceived.
If ACK is not received, stop communication.

(2) About transfer direction

When reading data from the slave, a 2-byte address is sent as data to the slave (EEPROM).
If nothing more is done, data reception does not start.
Such an operation is not possible as the I²C bus.
After specifying the EEPROM address, restart must be performed and communication must be restarted by data read.
Please check the specifications of the EEPROM that is used.

The processing flow described in the manual for the uPD780034AY is programmed as shown below, but stop conditions cannot be detected.

    PM3.2 = 1;           /* Sets alternate ports */
    PM3.3 = 1;
    P3.2= 0;
    P3.3= 0;

    IICCL0.3 = 0;        /* Sets operation mode */
    IICCL0.2 = 0;
    IICCL0.0 = 0;
    IICE0 = 1;           /* Sets I2C control register 0 */
    WTIM0 = 1;           /* Sets interrupt timing */

    PM3.2 = 0;
    PM3.3 = 0;

    SPT0 = 1;            /* Generates stop condition */
    while (SPD0 != 1) {  /* Detects stop condition */
    }

This is caused by the bit manipulation that is performed to set the alternate ports.
When P3.3 = 0 is executed, the P3.2 status is "1" as an external pin's status ("1" is read due to pull-up by the input port), so the SDA0 (P.32) value keeps "1".

Consequently, it is not possible to generate a stop condition (at the rising edge of SDA0 when the SCL0 pin value = 1).
To resolve this problem, either the set ports in byte units or execute "P3.3 = 0;" after setting the PM register to output mode.

Also, be sure to note the section entitled "Cautions Regarding Bit Manipulation" included in this FAQ.

I am trying to use the uPD780034AY to control the I²C bus, but I cannot get any farther than transmitting the address.

    do{
        IIC0 = 0B10100000;    /* Sets address and direction */
        do { NOP();
        } while ( IICIF0 == 0 );
            IICIF0 = 0;
    } while ( ACKD0 == 0 );

To resolve this problem, stop using the ACKD0-confirming loop.
With the I²C bus, if an ACK is not returned as a response, it should be assumed that there is no slave device corresponding to the transmitted address.

In the program submitted with your question, ACKD0 detection sets a loop whereby the address is sent again.
But this time it is not interpreted as an address, so an ACK is not returned.
Before resending the address, be sure to issue a start condition.

In the uPD784031Y, why does the clock frequency set by the prescaler differ from the frequency that was actually observed on the bus?

The frequency that can be set is the one that corresponds to a signal rise time of zero.
In the actual bus, the rise time may be slowed depending on the bus's capacity.
When such slowing occurs, the frequency value observed on the bus may be lower than the set frequency.

I am using the uPD784031Y to control the EEPROM via I²C.
I am able to read the EEPROM without any problem, then I issue a stop condition to stop processing.
But when I subsequently issue a start condition, SDA will not go to low level.

It seems that after setting a stop condition, you are issuing a start condition without confirming that the stop condition was actually issued.
Always confirm issuance of a stop condition or start condition before proceeding to the next processing.

What is the simplified I2C of the 78K0R/Kx3?

This is a serial interface that has only functions as a master in the single master mode of the I2C. Since the wait function is not supported, slow slaves cannot be connected.