Clock

In the uPD780031A, the minimum instruction execution time is described as being changeable between high speed (0.4μs) and low speed (1.6μs).
How can the minimum instruction execution time be changed?

The instruction execution time can be changed by switching the CPU's operating clock using the PCC register.

In the uPD780024A, the resonator is described as "up to 8.38MHz" in the shipment specifications.
However, in the User's Manual (section on UART in CHAPTER 16 SERIAL INTERFACE), the main system clock resonator is described as up to 8.386MHz.
There is a difference of 0.006MHz, but can a 8.386MHz resonator be used?

Yes.
The operation is actually up to 8.3886MHz, which is double 4.1943 MHz, but the figure is rounded off, resulting in 8.38MHz.

Regarding the oscillation stabilization time of the uPD780024's main clock (ceramic resonator), when the oscillation frequency is 8.38MHz and a reset is input, does the oscillation stabilization time become 15.6ms according to OSTS?

Yes, this is correct.

The electrical specifications section in the data sheet indicates that the oscillation stabilization time when using a ceramic resonator is 4 ms.
However, the reset function explanation says, "after the oscillation stabilization time has elapsed (2 ¹⁷/fx)".
Why are these times different?

The value in the electrical specifications prescribes the characteristics of the oscillator.
In other words, as long as there is matching, when using a ceramic resonator, oscillation of the internal oscillator will stabilize within 4 ms.
On the other hand, 2 ¹⁷/fx applies to the microcontroller as a whole and indicates the time required for oscillation to stabilize before the CPU can start operating.
If this value is longer than the actual stabilization time of the oscillator, the clock oscillation is already stable by the time the CPU starts operating, so there is no possibility of malfunction due to the oscillation stabilization time.

In the uPD789488, when the main system clock and subsystem clock start operating via a power-on reset, does the oscillation stabilization time ( 2 ¹⁵ / fx ) include that of the subsystem clock?

No.
The oscillation stabilization time of the subsystem clock is not considered for this oscillation stabilization time.
If the oscillation stabilization time of the subsystem clock is needed, please wait using software.

The above says that


What is the method for securing it?

One method is to use the interval timer function of the watch timer.
In this case, select the subsystem clock as the clock source with the WTM register, start the watch timer, and wait for the INTWT1 interrupt request flag (WTIIF) to be set by a 9-bit counter overflow.

On p.283 of the User's Manual it says,

Does this concern the main system clock?
Is an even longer oscillation stabilization time needed for the subsystem clock?

Yes, this is correct.
Normally, the oscillation stabilization time is shorter for the main clock, which has a higher frequency, than for the subsystem clock, which has a lower frequency.

Therefore, if just this "2 ¹⁵ / fx" is waited for after reset, stabilization of the subsystem clock oscillation will not occur.
Note also that the subsystem clock does not stop oscillating even during reset.

Regarding the switching time from the uPD78011 subsystem clock, I want to switch instantly from the subsystem clock to the main system clock by program.
Is this OK?

It is not possible to instantly switch from the subsystem clock to the main system clock.
Normally, when resuming oscillation of the main system clock from the oscillation stopped state, a time of 4ms is required.
When instantly switching the clock by program, the switching time is less than 0.6ms, so the system clock is switched to before the oscillation stabilizes, causing a program loop due an abnormal clock.

Thus be sure to switch after a delay of the time specified by the OSTS register.

I would like to input the output of an external oscillator with a 3V power supply to the subsystem clock during 5V operation of the uPD78045. Is this possible?

When the power supply voltage of the CPU is 5V, and the subsystem clock pin's input level is 3Vp-p, the amplitude of the clock input is too small and the input voltage specifications are not satisfied.

The specifications for when the power supply voltage is between 4.5V and 5.5V are as follows.


Consider amplifying the output signal of the oscillator to obtain sufficient amplitude.

In the uPD784216, no subsystem clock is connected (XT1 = VSS), but an SFR has been set for counting the subsystem clock (WTM = 83H). Is this a problem?

There is no problem for the device.
However, this is an abnormal setting from the standpoint of program management, and if left as is, various problems are likely to occur during later maintenance.
It is therefore recommended to set the watch timer not to operate if it is not used.

In the uPD789046, I would like to enter the HALT mode after switching from the main system clock (4MHz) to the subsystem clock (32.768 kHz), and then release the HALT mode with an interrupt request from the 16-bit timer (select the subsystem clock as the clock), but HALT is not released.

This is likely due to device restrictions.
Try enabling buzzer output.

In the uPD789488, it is now possible to specify x8 (x4) multiplication of the subsystem clock using the subsystem clock selection register.
What kind of principle is involved in achieving x8 (x4) multiplication?
(Is multiplication performed even when the main system clock is stopped?)

Since an explanation of the internal circuits of the device is complicated, it will be omitted here.
Suffice to say that the main system clock is not used for multiplication, so multiplication is performed even when the main system clock is stopped.

In the uPD78P083, is the clock input to X1 and X2 divided for the main system clock oscillator shown in Figure 5-1. in the User's Manual?
When 5MHz (fx) is connected to X1 and X2, is 5MHz output for fx as is?

fx is 5MHz.

I wish to test the watch interrupt request flag register using an instruction in the main routine after entering the STOP mode in the subsystem clock operating status.

I can shift to the STOP mode after disabling servicing of the watch interrupt (setting the interrupt mask flag register), but when there is a watch interrupt in the STOP mode, can I assume that the CPU will start from the next instruction after the STOP instruction?

It appears that you basically have a number of misconceptions.

First, when the CPU is operating with the subsystem clock, there is no STOP mode.
(The subsystem clock oscillation cannot be stopped.)
When the CPU is operating with the subsystem clock, the main system clock oscillation can be stopped by a register setting.

Next, to release the standby mode, the interrupt mask (WTMK) related to the trigger must be cleared, that is to release standby, the interrupt must not be masked.
However, the CPU itself can be in the interrupt disabled state.

Probably to perform the operation you want, you need to start operation with the subsystem clock, stop the main system clock oscillation, clear WTMK, set the CPU to DI, and stop the CPU with the HALT instruction.

In this status, upon occurrence of a watch timer interrupt, HALT is released and the CPU restarts from the next instruction following the HALT instruction.

It is written that, in the power-on sequence for the uPD784216, instruction execution starts at the main system clock's minimum speed (2560ns: 12.5MHz) following reset.
Can this minimum speed of 2560ns be achieved using STBC and CC settings?

Yes.
But, CC cannot be cleared by software.
So, if CC is set, this minimum speed cannot be achieved using CC.
If CC is 0, setting STBC to 30H can achieve this minimum speed.

I am considering using the uPD78F9026A.
The clock input range is from 1MHz to 5MHz. Will the uPD78F9026A operate at 100kHz?

The operation at 100kHz is not guaranteed.
The operation can be guaranteed for the range from 1MHz to 5MHz described in the data sheet.
The uPD78F9046 has a subsystem clock that can operate in the range from 32 to 35kHz, so please consider using this product.

After entering STOP mode with bit 0 (MCM0) of the main clock register (MCM) set to 1 (X1 input clock), does the system restart operation on the internal oscillation clock for the next instruction after STOP mode is released by acknowledgment of an interrupt request?

No, it does not. The system will restart operation in the original state (X1 input clock).
The system will restart operation on the internal oscillation clock only after STOP mode is released by a reset.

After STOP mode is released, I want to operate the system on the internal oscillation clock until the oscillation stabilization time of the X1 input clock has elapsed.
In this case, do I have to clear bit 0 (MCM0) of the main clock register (MCM) to 0 (internal oscillation clock)?

Yes, you must.
However, in this case, be sure to stop the main clock by using the MSTOP bit of the MOC register.

When starting up the system without the X1 pin connected, I cannot execute a reset even though the clock monitor operation is enabled.

The clock monitor function will not operate unless the X1 clock is input.
Therefore, you cannot use the clock monitor function while the X1 pin is not connected.
Moreover, if you specify operation on the X1 clock when the X1 clock is not oscillating, the operation does not switch to the X1 clock operation but continues on the internal oscillator.

How can I detect a malfunction of the clock (X1) when the X1 clock is not being supplied?

To detect that the X1 clock is not oscillating, operate timer H with the internal oscillation clock, and check the value of OSTC.
If it does not change for a certain period of time, you can conclude that X1 oscillation malfunction.

When the main clock frequency is output from the PCL pin, does a frequency error occur due to the division processing?

No clock output frequency error occurs in this case.
Fluctuation in the clock output frequency can be caused only by a variation in the oscillation frequency of the clock itself.

Oscillation of the main clock stops even though I have not executed a STOP instruction.
I do not think there is a problem with the program as it has already been checked using an emulator.

Is there oscillator matching?
Normal oscillation cannot be obtained unless there is oscillator matching.

I am using a blank uPD78F0034B and have embedded an oscillator with the specified constants at X1 and X2.
But when I evaluate the clock oscillation, the oscillation stops after only a few seconds.

If there is no problem with the oscillator matching and the clock oscillation stops even though it has not been stopped by the program, possibly there is noise on the reset pin.
The main clock oscillation stops during a reset, so you should check the reset line.

This concerns the subsystem clock of the uPD78P058Y.
When I set as follows to switch operation from the subsystem clock to the main clock, subsystem clock oscillation does not seem to stop.

     clr1   MCC
     clr1   CSS

Subsystem clock oscillation cannot be controlled in the 78K0 Series.
When not using the subsystem clock, the feedback resistor can be disconnected to reduce power consumption, but oscillation of the subsystem clock cannot be controlled.

Remark
The 78K0S Series includes products in which oscillation of the subsystem clock can be controlled.

During a noise test, the microcontroller program looped and the clock stopped about three times.
Other than the microcontroller entering STOP mode due to the program loop, is there any other reason for the clock oscillation to stop like this?

The noise may have caused the operation of the oscillator itself to malfunction, stopping oscillation.
It is not possible to specify how a microcontroller that has malfunctioned during a noise test will operate.

When changing the system clock from the subsystem clock to the main system clock, how many clocks should I wait for the oscillation to stabilize after setting MCC to oscillation enabled?

You do not need to wait at all.
When operating on the subsystem clock, the main system clock using RC oscillation will stabilize by the time the clock switches after oscillation is enabled by clearing the MCC bit.
Therefore, there is no particular need to program an oscillation stabilization wait time; you can switch the clock immediately after enabling oscillation.

Although 3.3 V is supplied as the power supply of the 78K0R/Kx3 and a ceramic resonator is connected to the X1/X2 pins for clock oscillation, measurement of the voltage of the X1 pin results in only 2.5 V. Is this OK?

In the 78K0R/Kx3, since the power generated by the internal regulator is supplied to the oscillator, the amplitude of the oscillator corresponds to the voltage of the internal regulator. So yes, this is OK.