Asynchronous SRAM

The configuration of a basic SRAM memory cell circuit is shown below.
A basic SRAM memory cell consists of two ring-shaped inverters and has two stable states in which data is held: A = L, B = H, or A = H, B = L. N-ch transistors are also connected to the bit lines in order to carry out read and write operations.



[Read operation]
N-ch transistors T1 and T2 are turned on when the word line of the RAM cell selected by an address becomes H.
The data held by inverters I1 and I2 is then output via T1 and T2 to the bit lines. This data is received by the sense amplifier to which the bit lines are connected and output externally.

[Write operation]
N-ch transistors T1 and T2 are turned on when the word line of the RAM cell selected by an address becomes H.
Data previously written to a buffer that has a higher drive capacity than that of RAM cell inverters I1 and I2 is then output from that buffer to the bit lines and forcibly written to inverters I1 and I2.

[Data retention]
Since SRAM uses inverters to hold data, the data continues to be held as long as power is supplied.
SRAM is a volatile memory in which the held data is lost if the inverters stop operating normally due to a drop of the power supply voltage.
Just after power is applied, it is not known whether the values of RAM cell inverters I1 and I2 may be L or H; these values are undefined.

[Current consumption]
The current consumed while data is held is only leakage current, and is no through current due to RAM cell inverters I1 and I2 being completely ON or OFF in the case of CMOS inverters.
Note that, generally, two types of SRAM are available depending on the application: low-current consuming "low-power SRAM" and "high-speed SRAM."

Aside: Different inverter configurations Two types of inverters are used for SRAM cells, as shown in the figure below: NMOS inverters and CMOS inverters. SRAM cells that use NMOS inverters have "4Tr2R" configuration, and have a smaller surface area because only N-ch transistors and high-resistance polysilicon are used; there are no P-ch transistors. However, because current flows through resistors when the inverters are ON, the current consumption is that much higher. On the other hand, SRAM cells that use CMOS inverters have "6Tr" configuration, known as "full CMOS", and although their surface area is larger, the current consumption of these memory cells is only leakage current.

(2006/04)

How does the data retention mode of low-power SRAM differ from standby?

In standby, the power supply voltage is in the operating range, but the SRAM is simply not being accessed and read/write operations are not being performed. So, read/write operations can be performed at any time.
In data retention mode, the power supply voltage drops below the standby level just to hold data in all SRAM cells. In this mode, the power supply voltage is below the operating range, so read/write operations cannot be performed. However, since the power supply voltage is lower, so is the power consumption.
Specifically, setting /CE1 = H, CE2 = H or CE2 = L in the uPD431000A are the same both on standby and on data retention mode.
As is described in Remark on page 20 of the uPD431000A Data Sheet, the conditions are applied to the CE2 voltage in the data retention mode by controlling /CE1, whereas /CE1 can be set to Hi-Z in the data retention mode by controlling CE2. There are no particular conditions that are applied to addresses, I/O, /WE, or /OE.

(2006/04)

In Low VCC Data Retention Characteristics on page 19 of the uPD431000A Data Sheet, the input level specifications, /CE1≥V_CC-0.2V, CE2≤0.2V, have become stricter. Why is that?

In the "L" version of the uPD431000A, the specifications are as follows.

	Power supply voltage	VIH(MIN.)	VIL(MAX.)
Standby state	4.5V to 5.5V	2.2V	0.8V
Data retention mode	2.0V to 5.5V	VCC-0.2V	0.2V

This is because when the power supply voltage falls to 2 V in data retention mode, this value is below the normal operating range specification of V_IH (MIN.) = 2.2 V. The input level specification has therefore been prescribed separately to avoid this.
Another reason the input level is restricted to within 0.2 V of V_CC and GND is to avoid through current flowing to the input pin's CMOS inverter; the power supply current can be restricted in data retention mode by keeping the input level value close to the V_CC and GND values.

(2006/07)

In Data Retention Timing Chart on page 20 of the uPD431000A Data Sheet, V _CCDR (MIN.) is smaller than V_IH (MIN.); does this mean that the power supply voltage is lower than the input level?

As explained in A2 above, V_IH (MIN.) = 2.2 V is the specification of the power supply voltage in the normal operating range.
When V _CCDR (MIN.), which is the power supply voltage in data retention mode, is 2.0 V, V_IH(MIN.) is 1.8 V.

(2006/07)

Is there any problem if signal A17 is input to the NC pin (pin 9) of the uPD431000AGU-B10X-9JH?

No.
Any signal may be input to the NC pin, as long as the signal level is within a reasonable range such as the supply voltage range, because this pin is not connected anywhere internally

It is noted "Determine the address at the same time as or before inputting a low level to /CS."
in Read Cycle Timing Chart 2 (/CS access) of AC Characteristics in the Data Sheet.

Is only the address accessed if a change in the address is slower than /CS?

That's right.
There is no priority in sequence for inputting the /CS and address signals.
In the Data Sheet, this "Caution" is inserted to define /CS access or address access.

That does not mean that malfunctions occur if one of them is input first.

Because of the specification of the microcontroller, the signal input to /UB, /LB, and /OE exceeds the specification limit of 15 ns max. after /CS has gone low.
It seems, from the table of operation modes, that data is output when all of /CS and /UB, /LB, and /OE are satisfied.

Is the timing a maximum of 7 ns after /UB, /LB, and /OE have gone low?

/UB, /LB, and /OE are signals that control the output buffer and do not operate until /CS goes low.
Even if this condition is satisfied, however, data is not output unless an address is determined because the output data has not reached the output buffer.

In other words, data is output if tAA after an address is determined and tACS after /CS goes low are satisfied, and if tOE and tABD are satisfied.
By this access method, tACS is satisfied after /CS goes low if a 15-ns product is used.
The problem is the timing of determining the address.
Assuming that determining address is delayed 13 ns from /CS, the 15-ns product outputs data after 15 ns. If /UB, /LB, and /OE are input after 15 ns, data is not output until 13 ns have passed since (this is because the data is not ready after 7 ns).

With asynchronous SRAM, is it possible to execute continuous access by switching addresses while /CS, /OE, and /WE are active?

Asynchronous SRAM can be read while /CS and /OE are active (defined as address access), but not written.
Unlike synchronous SRAM, asynchronous SRAM does not have a structure whereby addresses are sampled based on a clock. Consequently, there is a danger that a misalignment in the timing of switching address lines may cause the other address data to be damaged.

(2008/01)