Synchronous SRAM

The specifications of synchronous pipeline SRAM include:
  SINGLE CYCLE DESELECT
  DOUBLE CYCLE DESELECT
  PIPLINED BURST
  FLOW THROUGH
What do these items differ and how should they be respectively used?
Also tell me the difference between linear and interleave burst.

In answering this question, the following abbreviations are used.
PIPLINED BURST : PB
FLOW THROUGH : FT
SINGLE CYCLE DESELECT : SCD
DOUBLE CYCLE DESELECT : DCD

Basically, the difference between PB and FT is whether or not an output register is provided.
The difference between SCD and DCD is whether data goes into a high-impedance state after 1 clock or 2 clocks if the output is disabled by the /CE signal (refer to the figure below).



PB and FT, and SCD and DCD belong to different categories.
Both SCD and DCD exist for PB, but only SCD exist for FT.

Let's discuss the difference between PB and FT in more detail.
The write cycle is the same for both, and an address (external or internal address) and data are captured in the same cycle.
When data is read, it is output for FT in a cycle next to the one that inputs an address, but, for PB, it is output in a cycle after 2 clocks.

It seems that FT is better because data is output after 1 clock, but PB can support a frequency higher than FT.
Therefore, both have their own merits and demerits.

The usage of these respective items is not defined in particular and the customer should select the one that is best suited for the proposed application based on the differences outlined above.
Regarding linear and interleave burst, PB and FT were originally developed as the specifications of the cache of a CPU, and either may be selected depending on how the CPU increments addresses. You may select either based on which one best-suits your purpose.

In the following timing chart of single read/write cycle on the Data Sheet, D1 is written to A5 at a clock next to the one at which Q1 is read from A4.
Can I/O of the data bus be switched with 1T (next clock) in this way?

Yes.

Q1 is read from A7 2T after D1 is written to A7. Is this D1 (A7) the same in value as Q1 (A7), or is it different?

It depends on the following Path Through Truth Table on the Data Sheet.
If the timing is as shown on page 15, the data same as that written is read.

What will happen to the address if the clock is kept input while the uPD432232L is executing burst transfer?
For example, if the transfer is suspended by inputting CLK for FFFF times before it is suspended with the start address = 0000, does the address return to 0000 again?
Or, is there specification of the number of times of burst?

This product is a pipeline burst SRAM developed as a cache for a PC, and the burst length is defined to be 4.

If Continue Burst is continued more than once following Begin Burst, the data that is output during a read operation and the addresses to which data is to be written are as follows.

1. Begin  Burst          External address
2. Continue  Burst        Internal address 1
3. Continue  Burst        Internal address 2
4. Continue  Burst        Internal address 3
5. Continue  Burst        Internal address same as the first external address
6. Continue  Burst        Internal address 1
7. Continue  Burst        Internal address 2
    •                        •
    •                        •
    •                        •
The first address is captured by Begin Burst (1) and the address is advanced to the next internal address by Continue Burst (2, 3, 4, and so on) in accordance with the table of interleave burst or linear leave burst.
At the fourth Continue Burst (refer to Burst Sequence on page 4 of the Data Sheet), the address returns to the internal address same as the first external address, and it is internal address 1 at the next Continue Burst.

To read or write data from start address = 0000 to FFFF as in the example, control must be performed in the sequence of Begin - Continue - Continue - Continue - Begin - Continue - Continue - Continue, and an address must be input from an external source at each Begin Burst.

The operation to be performed if the ZZ and MODE pins are opened is shown on the following tables in the Data Sheet. Can the uPD432232L be used while these pins are open?

Internally the ZZ pin is slightly pulled down and the MODE pin is slightly pulled up. When they are open, the pull-down and pull-up resistance values are very high, despite the assumption that low is input to the ZZ pin and high is input to the MODE pin.
If these pins are open, the uPD432232L is likely to be affected by the external circuit. Therefore, externally connect these pins to V_DD or V_SS.

Can the uPD4382361 successively read data by incrementing the address at each clock, while the Synchronous Address Status Processor Input (/AP) signal is fixed to the enable level?

It is possible to read data successively.
Data can be successively read by capturing an external address at each clock by Begin Burst when /AP = L.

In the same manner as above, with regard to the write operation, can data be successively written by incrementing the address at each clock with the Synchronous Address Status Processor Input (/AP) signal fixed to the enable level?

No, it cannot be written.
In this case, data can be successively written by using Begin Burst.
While /AP = L, an external address cannot be latched by Begin Burst, and data cannot be written to a specific address.

How should /AP and /AC respectively be used?

Both /AP and /AC are signals to latch an address.
/AP has one additional NAND

(refer to the block diagram from the Data Sheet below).


/AP: Address status processor input (CPU controls latching of an address (whether it is latched or not).)
/AC: Address status controller input (The chip set (controller) controls latching of an address (whether it is latched or not).)

When using the uPD4382361 in a set other than a PC, design the set by referring to the truth table and timing chart, to ensure that there will be no problems.

Can an access of the same timing be performed even if the second of successive single accesses and those that follow are controlled with /AC = H and /ADV = L?

In this case, an external address is not captured because the second access and those that follow are suspend burst.
When data is read, therefore, the data of an address same as the one previously latched is output.
When data is written, it is written to the same address as the one previously latched.
Although the uPD4382361 does operate, the operation is almost meaningless.

We are considering use of the uPD4382361. Is it all right if the 4 bits of I/OP (4:1), parity bits, are used as data lines in the same manner as I/O (32:1)?

Yes. They can be used as data lines.

Is there any product with 8M (data bus: 36 bits) SSRAM that can perform read → write accesses without wait time?
(Products of other manufacturers such as NtRAM (Toshiba, Samsung), ZBT (Micron, IDT), and NoBL (Cypress) are available. Does NEC Electronics offer equivalent products?)

A product compatible to NtRAM (Toshiba, Samsung), ZBT (Micron, IDT), and NoBL (Cypress) is available from NEC Electronics with the product name of ZEROSB SRAM.

What is Late Write synchronous SRAM?

An operation to write data in a cycle next to the one in which an address is input to a synchronous memory is called a Late Write operation, and synchronous SRAM that uses this operation as a basic operation is especially called Late Write synchronous SRAM.

What are the differences between standard synchronous SRAM and Late Write synchronous SRAM?

The major difference in circuit configuration between standard synchronous SRAM and Late Write synchronous SRAM is that Late Write synchronous SRAM has a "Write Address Register".

This "Write Address Register" is used to save an address to the write address register once even if an address or control signal for read operation is input in a cycle in which written data is to be input.
operation can be completed by using the address of the Write Address Register after the read operation has been completed.
This operation can reduce the number of wait cycles when repeating read → write → read, and so on.

What is ZEROSB SRAM?

It is high-speed synchronous SRAM ideal for the buffer memory of network equipment that does not cause a dead cycle when the operation is switched between read and write.
ZEROSB is a trademark of NEC. The other manufacturers that supply this SRAM call it "ZBT™ SRAM" or "NtRAM™".

ZBT is a trademark of IDT.
NtRAM is a trademark of Samsung Electronics.

What is the difference in operation between standard synchronous SRAM and ZEROSB SRAM?

Standard synchronous SRAM requires a wait cycle between a read cycle and a write cycle if operation cycle read → write → read, and so on, is repeated, because the standard synchronous SRAM performs write data input in the same cycle as address input.

ZEROSB SRAM has a Write Address Register, like the Late Write synchronous SRAM.
In this regard, ZEROSB SRAM has specifications based on which the concept of the Late Write Synchronous SRAM was developed.

The flow through version of ZEROSB has a Write Address Register of one address, and the pipeline model has a Write Address Register of two addresses.
The operation of this Write Address Register can completely eliminate wait cycles when an operation is performed from read → write → read, and so on.

Because a memory does not always alternately perform read and write operations, standard synchronous SRAM or ZEROSB SRAM is used depending on the purpose.

The block diagram of the Data Sheet of the uPD4481322 shows two stages of a data input register.
If data (D1) is written to an address (A1) and if the same address (A1) is read in the next cycle, is the read data (D1), or the previous value (D0)?

The read data is D1.
If the same address is read in a cycle next to a write cycle, data has not yet been written to a memory cell, but it is judged that the address is the same, and the data of the data input register is output.