LCD Driver

When the operation is executed as described in "Application" of the uPD16430A Data Sheet, does BUSY output become low after the writing data n and rising edge of the STB input?

Yes, it does.

When a key is pressed for a split second only, KEYREQ becomes HIGH, but when key data is read, are there times when the key data goes into the state of nothing being pressed?

Yes, there are.

What do character codes 0x8b, 0x8c, 0x8d, 0x9b, 0x9c, and 0x9d define?

These are special European characters.

The pictograph display segments are driven by the uPD16432B, but what is the method for accessing addresses of the RAM for pictograph display?

Pictograph display refers to character display.
When reading 4.11 Commands in the uPD16432B Data Sheet, replace "character display RAM" with "pictograph display RAM".
In other words, in the mode setting, specify "001: Write to character display RAM," and set the addresses range to "00H to 07H."

The power-on sequence is the order of suppling -10 V to VSS, 5 V to VCC, +15 V to VDD1, and 0 V to VDD2, and then input of a pattern to BI1. GND, NC, and SUBI become 0 V at power-on (of VSS).
At this time, three-value output is performed to the two-value output block. Is such a thing possible?

In the case of this product, the internal comparator becomes floating if VCC is not applied, and as a result normal operation is not performed. Regarding the phenomenon described in the question, there is a problem in the power-on sequence, and the phenomenon is probably caused by unstable output. Use the following power-on and power-off sequences.
• Power-on sequence
  1. First, apply VCC.
      At this time, input pin (TIx, PGx, BIx, SUBI) voltage ≤ VCC.
      Moreover, when Vsb = 2 V, VCC must be applied within the prescribed voltage
      (recommended range: 2.0 V to 5.5 V).
  2. Next, apply Vsb, VDD1, VDD2a, VDD2b, and Vss
      At this time, SUBI must be high level (0.8 VCC or higher).

• Power-off sequence.
  1. Cut off Vsb, VDD1, VDD2a, VDD2b, and Vss.
      SUBI must be high level (0.8 VCC or higher) until VCC is cut off.
  2. Cut off VCC.
      Cut off VCC when Vsb has become 2 V or lower.
      At this time, input pin (TIx, PGx, BIx, SUBI) voltage ≤ VCC.

I want to set the oscillation frequency to 80 kHz with an external resistor, but what is the method for calculating that resistor value?

There is no calculation method, but if the power supply is 5 V and the external resistor is set to 300 kΩ, the oscillation frequency can be set to approximately 80 kHz.

The uPD160061A Data Sheet says that this driver is applicable to SXGA-standard (1280 × 1024 pixels) TFT-LCD panels.
Does this mean that 60 frames can be displayed in one second even when VDD1 = 2.3 V and the data transfer clock is at 40 MHz?

Yes.
Because two pixels (× 6 bits × 3 (RGB)) can be input in one clock, the number of display clocks of one horizontal period is 1280/2 = 640.
It takes at least five clocks after inputting data of one horizontal period has been completed until the next data can be input (until STB rises and the start pulse rises).
Therefore, the minimum data transfer clock frequency is (640 + 5) × 1024 × 60 = 39.6 (MHz).

(2006/10)

Why can't the data sheets for most of the LCD drivers be downloaded from the NEC Electronics website?

Most LCD driver packages are TCPs and the TCPs are designed with custom specifications, so documents for these LCD drivers are distributed through distributors. We apologize for the inconvenience, but consult your nearest distributor.

(2007/08)