CCD

The position of the 1st effective pixel is indicated in the datasheet of the uPD3719.
Is the distance between the 1st effective pixel position and the 10600th pixel position 72.8 mm calculated from the center line?
Or is it 74.2mm (= 7um x 10600) calculated from the 1st pixel?

It is the latter (74.2 mm).
The position of each pixel is obtained by multiplying the pixel (cell) pitch and the number of the pixel (cell), using the 1st effective pixel as reference.
In other words, it is the relative position from the position of the 1st effective pixel.

A value of 800 nm or higher is not indicated as the total spectral response characteristics in the data sheet, but is there spectral response at wavelengths over 800 nm?

Data was measured using a product which happens to be at hand.
So, this data is showed as following for reference purposes only and does not represent any guarantee.

When a uniform light is projected onto a CCD, a few (approx. three) consecutive even or odd pixels are sometimes output at the low output level.
Are there specifications regarding the maximum number of consecutive non-uniform pixels?

No, there are no specifications regarding non-uniform pixels.
As listed in the data sheets, the specification on the non-uniformity (PRNU) of the output voltage specifies the maximum or minimum level of non-uniform pixels among all effective pixels as percentages of the average output level.

Factors that cause PRNU degradation in this products themself include uneven coating of the on-chip filter, but products with degraded PRNU are filtered based on the PRNU rating and products whose non-uniform level exceeds the specifications are not shipped out.

(However, as noted above, there are no specifications regarding consecutive pixels, and even if the output level of non-uniform pixels is within the ratings, this does not mean that there are no consecutive non-uniform pixels.)

External factors of the products that may lower PRNU include scratches or dirt on the glass cap.
Output of consecutive non-uniform pixels may be caused depending on the size of the scratches and dirt.

Is a cover which is attached to the sensor part in the actual product a protection seal?
Should this cover be removed during use?
Also, is this cover always attached on this part?

Yes, the cover on the plastic package of CCD is a protection seal.
This protection seal serves to protect the plastic and should be removed when the CCD is used.

The latest CCDs (which come in a plastic package) are all provided with a protection seal.
The uPD3734ACY, which has been manufactured for a long time, can be ordered without a protection seal.
However, since the plastic cap is easily scratched, the purchase of products with a protection seal is recommended.

When a spot-like high luminance image is input, a phenomenon called blooming will occur, whereby even peripheral pixels are saturated.
At which level does blooming occur when the saturation exposure range is exceeded?
Is there a specification regarding the maximum value of saturation exposure?

It has not been evaluated at which level blooming occurs if the saturation exposure level is exceeded.
Use CCDs at a level lower than that at which the output voltage is saturated (saturation output voltage MIN or lower).
There is no specification regarding the maximum value of saturation exposure.

Is it possible to reduce blooming without sacrificing sensitivity, such as by shortening the exposure time?

The ways to prevent blooming are to reduce the light intensity of the light source and shorten the storage time so as to use the CCD in a range in which it does not saturate (saturation output voltage MIN or lower).

Please let me know the definition and maximum value of Bit Noise.

Bit Noise is the most deviation from average level of output signals, and can be expressed by the following approximation formula:
 Pixel fluctuation (BN) ≡ 5 x Random noise (σ)
For details on random noise, refer to page 12 of the data sheet.

The measurement conditions (other than calculation) are the same for random noise and Bit Noise.
The Bit Noise specifications are provided as reference values, and only the typical values are listed.
There is no specification regarding the max. value. The merit value of fluctuation is approx. 9 to 11 mVP-P.

Is it OK to stop the pulse, such as the shift register clock, while the CCD power is on?
Also, what is the operation when the pulse is re-started?

Device destruction or latchup does not occur even when the input pulse is stopped.
However, in a state where no pulse is applied, the electric charge of the CCD will overflow.

Therefore, when the pulse is re-started, normal output cannot be obtained before drive pulses for a dozen to several tens of scans have been applied.
The number of scans before valid output can be obtained depends on the state (presence/absence of optical input, the time) in which the product is placed from when pulse input stops until it is re-started, and thus cannot be specified.

Design with a sufficient safety margin based on careful evaluation.

Is it necessary to provide the φRB and φSHB signals while the φTG signal is high level?
If yes, then what is the timing

To ensure normal circuit operation, it is necessary to provide φRB and φSHB while the φTG signal is high level.
φRB and φSHB should basically be kept as continuous waveforms even while the φTG signal is high level (as described in the data sheet, continuous waveforms consisting of the same signal).

Regarding the timing, observe the timing indicated in the data sheet, even while the φTG signal is high level.
(Also be careful to keep the timing with φ1 and φ2 (before and after φ1, φ2 stop))

Will the operation become abnormal if three or more pulses are provided to the φRB and φSHB signals while the φTG signal is high level?

As long as the frequency is within the range indicated in the data sheet, there is no problem.

Where is the output pixel number reference point?

As described in the timing chart on page 7 of the data sheet, the start of valid photocell 2660 pixels is used as the pixel number reference point.
The physical position of the 1st valid pixel is indicated in "PACKAGE DIMENSIONS" on page 15 of the data sheet.

Is temperature and photoreceiver output characteristics data available?

We have obtained this data for two uPD3739D units that were on hand at the time.
The data is available below for your reference.


  Data rate = 2MHz(1MHz/ch)
  VOD = 12V
  Input clock= 5V P-P
  * Daylight color fluorescent lamp sensitivity
  * The rate of change is indicated as 100% for the value at 25 °C

The wavelength in the response characteristic graph in the data sheet goes up to 350 nm only, but how are the response characteristic at lower wavelengths?

Since the spectral response characteristic indicates the characteristic of the signal output obtained according to the light wavelength, the longer the wavelength is, the deeper the location is in the CCD element board where the light is absorbed, and the shorter it is, the more shallow and near the surface the location is where the light is absorbed.

Therefore, longer wavelength light and shorter wavelength light in the invisible light regions are not sufficiently converted into electric charges, and in CCDs of a general structure, the response drops to a meaningless level.

As general characteristics, while the response on the longer wavelength side declines gently as shown in the following figure, on the shorter wavelength side, it drops abruptly.

When the light is incoming, does random noise becomes larger than that in light shielding?

Yes, random noise increases when the light is incoming against that in light shielding.
This is due the fact that random noise is caused by (A) and (B) below.
(A) Amplifier noise component (noise of the MOS transistors that make up the amplifier)
(B) Fluctuation component of signal charge (variation in the number of electrons resulting from photoelectric conversion)

(A) causes it during light shielding, (A)+(B) causes it during light incoming, so the random noise increases when the light is incoming.
Amplifier noise (A) is constant regardless of the signal amount.

Fluctuation component of the signal charge (B) is proportional to the square root of the signal charge amount (in other words, the signal amount).
The actual measurement values are reported as reference values. (Refer to the data sheet for definitions.)

****Measurement Data (Reference Values)****

Signal amount (V)	0	0.3	0.5	1.0
Random noise (mV)	0.7	3.3	4.1	5.0

During light shielding, the random noise consists only of the (A) component, but during the light is incoming, the (B) component becomes dominant.
The (A) and (B) values change also according to the measurement system's noise.
Moreover, the fluctuation component of the light source is of course an additional factor to the (B) component.

The above values are those obtained using NECEL's measuring system and light source, so they should be regarded solely as reference values.

The storage time is related to the signal amount.
Therefore, if the storage time doubles, so does the signal amount, and the (B) component becomes the double of the square root.

What kind of influence does phase lag of the crosspoint of two phase clocks, such as shift register clocks φ11 and φ21, have?
Also, should only the resistance be used for the fine adjustment method?

If the two phase clocks cross at a point where the voltage is low, the total transfer efficiency (TTE) of the CCD may be degraded and the transferred carrier may be reversed (back current). In addition, it also may cause a difference in voltage between Vout1 (odd) and Vout2 (even).

<1> Cause of TTE defect:
If the high-level width of the clock is shortened, transfer cannot be completed in time, and the frequency effectively exceeds the limits, a TTE (total transfer efficiency) defect may occur. There is no problem if the frequency is sufficiently low.

<2> Cause of back current:
Each bit of the CCD register consists of two gates, barrier and storage, to realize dummy three phases. The lower the clock voltage applied to the barrier and storage gates, the lower the potential difference under the two gates. Consequently, the charge may be reversed if there is a signal level close to the saturated output level. Of course, the charge may also be carried through the next gate.

<3> Cause of passing through the output gate
The CCD shift register has a gate called OG (output gate) in the final stage. If the crosspoint of the last gate and the preceding gate (e.g., φ2 and φ1L) is low, a passing-through phenomenon occurs where part of the charge accumulated at φ2, though all charge is supposed to stay under OG at φ1L, passes through the floating capacitor in the output stage.

Note that fine adjustments are recommended to be made by using only resistors (in series).

(2007/04)

Is it OK that approximately 100mV is difference between the Vout1 (odd) and Vout2 (even) outputs of the CCD from GND?

This is OK if the 100 mV potential difference between CCD outputs Vout1 and Vout2 is the offset level.
However, if you mean the signal level, there is a specification regarding register imbalance, and a difference of 100 mV is higher than value calculated from this specification (specification: 4% max. at Vout = 500 mV).

Register imbalance is defined on page 15 of the data sheet of this product as the ratio of the average values of the difference between the even and odd pixel outputs, and the average output voltage of all effective pixels, when a uniform light is applied.

Based on actual results, it is unlikely that register imbalance is excessive, but it is a possibility that it is worsened by the state of the crosspoint of the shift register clock.

What is the reset gate clock φR1 signal used for?

φR1 (reset pulse) is an indispensable pulse for the CCD's operation, and as its name indicates, it serves to reset the signal level, which changes due to the light for each pixel.
Therefore, if this pulse width becomes too short, reset failures occur, which may cause degradation in signal level, linearity, and resolution (MTF), etc.

Since the pulse width of φR1 is only 12.5 ns, is it OK to move the rising edge previously?

No, it isn't. If the rising edge of φR1 is moved to the front, the reset term encroaches on the signal output term, which may make signal output impossible.
Thus expand the falling edge side to the 15 ns of the specification or longer.

What kind of circuit is Automatic φR level adjuster?

Automatic φR level adjuster is a circuit that causes shifting the reset gate clock input (φR) to the appropriate level for resetting in CCD.

There are an odd output and an even output. When only one of these outputs is used, is it OK not to input a clock, etc., to the shift register for the other output?

The uPD3739 divides one row of photocells into two CCD analog shift registers and outputs them.
When the clock for the unused output is not input, an electric charge constantly stored in each of the unused photocells.

At last, the electric charge starts leaking from the photocells and may have an adverse effect by leaking to adjacent pixels.
Thus even when using only one of the outputs, input all the signals as indicated in the data sheet.

In this case, if an output is not used, doesn't the electric charge leak to that output?

As shown in the following figure, the output circuit performs output by converting the electric charge transferred with clocks φ1 and φ2 into a voltage.

Following its conversion into a voltage, the electric charge is reset by the reset gate clock, so the electric charge does not store.
Therefore, the output can be left open.

I want to use about 1,500 pixels in order to raise the refresh rate, but is this possible?
Is light-sheilding a required condition for the unused area?

Since the detailed timing is unknown, a clear answer is not available, but inputting φTG before completing transfer of 5,000 pixels and reducing the time by the equivalent of one line is not recommended.

This is because, in the case of such use, the output of the unused pixels and the output of the used 1,500 pixels get mixed.

In the data sheet, Remark 2 under APPLICATION CIRCUIT EXAMPLE (Out of phase operation) says

Does this mean whether pins 17 and 6 should be driven with a different IC, or they can be driven with a different gate of the same IC?

This means that pins 17 and 6 should be driven with a different IC.

Since the pins for shift register clocks 1, 2 (φ11, φ12, φ21, φ22) have a large input capacitance, which results in a large drive current, making the drivers for these pins and drivers for the last stage shift register clock (φ1L2, φ2L1) the same IC is not desirable because the last stage shift register clock, which determines the stable term of the CCD output, becomes influenced by the shift register clock.

Therefore, driving pins 17 and 6 with a different IC is recommended.
In Application Circuit Example, the inverter is enclosed in dashed lines, but consider that this representation is used for the sake of convenience to indicate the connection of the power supply and GND of the inverter.

Does driving all the shift register clocks 1, 2, (φ11, φ12, φ21, φ22) with the drivers of the same package cause any problems?

There are no problems in particular as a CCD as long as the specifications are satisfied.

One potential problem, which depends on the board pattern of the customer, is that since the shift register clock pins are divided on both sides of the CCD package, if driving all the shift register clocks 1, 2 with the driver of a single package, it may be more difficult to satisfy the crosspoint specifications, particularly for higher frequency, by routing pattern of the inverter output.

Should different packages also be used for shift register clocks 1, 2 (φ11, φ12, φ21, φ22) and φTG, φR1, φR2?

There is no recommendation in particular other than that described in A1 above.
Whether to use the same package for shift register clocks 1 and 2, basically depends on the magnitude of the influence of noise from the shift register clock.

Therefore, it is not possible to give a cut and dried answer, as this depends on the environment, such as the pattern designed by the customer.

Do the 50%, 90%, 10% in TIMING CHART 2 in the data sheet mean 2.5 V, 4.5 V, and 0.5 V?
Or are these percentages for the difference in potential between the H level and L level of the actual driving waveform?

They mean the latter. In other words, these percentages indicate that for the difference in potential between the H level and L level of the actual driving waveform (within the recommended operating range).

Regarding times such as t1 listed in the table on page 9 of the data sheet, only the Min. and Typ.
values are listed, but not the Max. value. Does this mean it is not a problem if the Typ. value is exceeded?

Basically this is not a problem as concerns the operation.

However, a point of caution is that if the falling edge of the last stage shift register waveform becomes late, the stability period of the CCD output becomes shorter, as indicated in TIMING CHART 2, so that the waveform of the last stage shift register clock should be kept as sharp as possible.

Which part of the timing chart does the storage time correspond to?

The φTG repetition period corresponds to the storage time.
Strictly speaking, it is the period from the falling edge of φTG until the next falling edge.

At what timing is the stored electric charge discharged?

It is discharged during the high level period of φTG.

Is a storage time of 100 ms a problem?

While there is no prescribed value for the storage time per se, there is one for the saturation voltage, and it depends on the exposure amount, in other words the storage time x intensity of illumination. The linearity of response is lost if the saturation voltage is exceeded. Further, the dark signal non-uniformity (DSNU value) grows in proportion to the storage time.
The rated value for the electrical characteristic of dark signal non-uniformity (DSNU value) is the value under condition of a storage time of 10 ms.
By the way, during evaluation and design, it is recommended to adjust the intensity of illumination (and storage time) so as to set the maximum possible exposure amount that is as close as possible to the saturation voltage, to obtain a wide dynamic range.

(2006/11)

The data sheet has a 2-dimensional photocell configuration diagram, but what is the 3D structure like?

The 3D structure of a photocell is as shown in the following figure.

What is the reset feed-through level clamp clock (φCP)?
Also, what is the difference between the signal outputs of Bit clamp mode and Line clamp mode?

The reset feed-through level clamp clock (φCP) is a timing pulse for performing clamping in the CCD.
There are two modes of clamping, Bit clamp mode and Line clamp mode.
Regarding the difference between signal outputs of Bit clamp mode and Line clamp mode, both modes of clamping are identical function-wise.
They clamp the CCD output to a set level.

However, the random noise characteristics in Bit clamp mode and Line clamp mode differ.
As shown in the electrical characteristics listed in the data sheet, the random noise in Line clamp mode is approximately four times (Typ.) larger than that in Bit clamp mode.
The clamp pulse is easier to be generated for Line clamp mode than for Bit clamp mode, but Bit clamp mode is recommended on account of the noise characteristics.

Moreover, in Bit clamp mode, noise caused by the clamp pulse is superimposed on the output waveform.
As comparison of the CCD output waveforms in TIMING CHART 2 (Bit clamp mode) and TIMING CHART 3 (Line clamp mode) of the data sheet, one can see that noise is superimposed on the output signal at the clamp pulse timing in Bit clamp mode.

There are both an analog and a digital GND pins, but in APPLICATION CIRCUIT EXAMPLE of the data sheet, they are connected with the same ground line together.
Is it necessary to separate one from the other?

No, it is not necessary to separate them, as shown in the application circuit example.
This is provided for the case when the customer wishes to perform board design taking noise into consideration.
The digital and analog grounds can be treated as one line without problem.

Regarding Total Spectral Response Characteristics, which of the following are the graph measurement conditions?
(1) Constant light intensity, (2) Constant energy

The measurement condition is (2) Constant energy.

A data rate of 2 MHz max. is indicated in the data sheet, but there is no information for the pulse width of φ1, φ2.
Based on the fact that Vout outputs a signal once in one cycle of φ1, φ2, is the interpretation that the frequency of φ1, φ2 is 2 MHz max. correct?
Also, what are the pulse width specifications?

The maximum frequency of the φ1, φ2 clocks is 2 MHz (500 ns).
There are ratings for the rising and falling edges of φ1, φ2, but there are no ratings for the clock width.
However, 50% should basically be used as the clock duty.

Regarding the timing with φTG (φTG, φ1, φ2 TIMING CHART) of the data sheet, +5 specified as 650ns (min) is bigger value than 500ns (min) of the φ1 or φ2 half clock width, but regarding t5, this is limited to the φTG pulse period only.

In other words, while this is difficult to understand in the overall timing chart (TIMING CHART 1) shown in the data sheet, it is necessary to perform input so that the high-level and low-level periods of φ1, φ2 before and after the φTG pulse become long.

What material is the top resin cover made of?
Can the cover resin be cleaned with an organic solvent such as alcohol to wipe off fingerprints, etc.?

It seems that the top resin cover means the plastic cap for window, and thus the material would be ARTON.
When wiping the cap, it is safe to use the following solvents.

  Ethyl alcohol (EtOH)
  Methyl alcohol (MeOH)
  Isopropyl alcohol (IPA)
  N-methyl pyrrolidone (NMP)

Use of a substance other than the above-listed solvents may cause either physical and/or optical damage on the cap.
Moreover, when wiping the cap, use a soft and clean (dust-free) cloth (any adhering dirt or particles on the cloth may damage the cap.)

The uPD8827A has three power supplies, namely Digital power supply, Heat sink voltage, and Output unit drain voltage, but to which circuits are the Digital power supply and Heat sink voltage supplied?

The Digital power supply is the power supply pin for the internal digital circuits such as the clock driver that generates signals.
The Heat sink voltage is the power supply required for maintaining the potential on the rear side of the CCD chip connected to the metal heat sink for heat dissipation purposes.

(2007/02)

The application circuit example in the data sheet describes the use of three buffers arranged in parallel for driving φ1A, φ2A, etc., but only 1 buffer is shown, even though the value of the φTG1 input pin capacitance, 400 pF typ., is large.
Why is that?

Whereas in order for crosspoint specifications to apply for φ1A, φ2A, etc., the specifications in relation to other signals are relatively severe, the relationship with other signals of φTG1 is an unexacting one, so that the rising and falling edge requirements are relatively lax. Further, the φTG1 pulse width (t3) is extremely long from 1 us min. to 5 us max., one reason for the lax requirements regarding the falling and rising edges.
While only one buffer is represented in the application circuit example, it should be kept in mind that this is just one application circuit example. Each customer needs to perform design and evaluation taking into consideration the wiring capacitance and other factors in order to meet the specifications.

(2007/02)

Is a micro lens attached?

No, it is not attached.

Is detection possible when the light is applied at a 60 degrees-incidence angle?

Depending on an incidence angle of light, the amount of light on the light-receiving surface of the CCD is greatly diminished as compared with the case of vertical light incidence, resulting in attenuation of the output signal.

With regard to this attenuation, the question of whether light can be detected using a 60 degrees-incidence angle depends on the system design and thus there is no single answer.