RGB-System OSD LSIs (uPD6461, uPD6462, uPD6466, and uPD6467)

Can the dot clock be checked in the uPD6466?

Although the dot clock frequency can be measured by using the CLKOUT pin in the uPD6461 or uPD6462, the uPD6466 does not have this kind of pin.
In the uPD6466, the dot clock can be output from the BLK1 pin by connecting the TEST pin to VDD and transferring the test mode command shown below.

2-byte command (MSB)

D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
1	0	1	1	0	0	0	0	0	0	0	0	1	1	0	0

2-byte command (LSB)

D0	D1	D2	D3	D4	D5	D6	D7	D8	D9	D10	D11	D12	D13	D14	D15
0	0	0	0	1	1	0	1	0	0	1	1	0	0	0	0

Caution Use this command only for checking the dot clock.

(2006/03)

If the camera is switched to another, the character position changes slightly.
Is there any way to accurately match the character position?

- If each camera is in synchronization with the other

The character position will not change even if the channel is changed if an external clock synchronized with the horizontal sync signal is used as the dot clock of each device.
To input an external clock, set the dot clock control bit (OSC) to "1" by using the Initial Status Setting command.
Input the clock to the OSCIN pin and leave the OSCOUT pin open.

- If each camera is not synchronized with the other

A circuit that uses a PLL based on the horizontal sync signal by using VCXO, etc., for each channel and that adjusts the phase and frequency of the dot clock between channels with respect to the horizontal sync signal is required.
The circuit scale will increase.

When the external clock input timing is used, what happens if t_H-C is less than 30 ns (MIN.) (for example, when the Hsync rising edge and the external clock falling edge overlap (t_H-C ≈ 0 ns))?

An NEC Electronics OSD LSI uses Hsync for the horizontal control counter reset signal and uses the external clock for the horizontal control counter clock.
If the t_H-C = MIN. 30 ns rating cannot be satisfied, the Hsync rising edge and the external clock falling edge can overlap within the horizontal control counter depending on the arrival delay time difference of Hsync and the clock to the horizontal control counter (due to manufacturing variations and usage environment conditions such as the power supply voltage and temperature).
If the edges overlap, the timings of the cancellation of a counter reset due to Hsync and the count increment can overlap. Therefore, an unstable condition occurs in which the edge overlapped by the clock may or may not be counted as the first edge.
Actually, since both Hsync and the clock have a slight amount of jitter, the condition in which that edge is or is not counted is repeated. As a result, the horizontal display position shifts by one clock (one-dot horizontal jitter occurs).

(2006/03)

What does the synchronization protection circuit do?

Please refer to "2.3.1 Synchronization protection circuit" in the OSD LSIs User's Manual (S13197E).

(2006/03)

In the uPD6461 or uPD6462, when "dot clock: external clock input" is selected by using the mask option, can LC oscillation occur?

When "dot clock: external clock input" is selected by using the mask option, LC oscillation cannot occur.
When external clock input is selected, since the oscillation stage of the LC oscillation circuit is completely disconnected from the pin (see (b) in Figure 2-2 Dot Clock Oscillation Equivalent Circuit in the OSD LSIs User's Manual (S13197E)), even if an external LC oscillator is attached, it cannot be made to oscillate.

(2006/03)

Are there any limitations concerning the clocks that are input when an external clock is selected?

Input an external clock using the following parameters as a guide.
  Input high level voltage = 0.7V_DD (MIN.)
  Input low level voltage = 0.3V_DD (MAX.)

Duty ratio: Set to 50% (TYP.)
At worst, make the dispersion range within 40 to 60%.
For information about the external clock fall → synchronization signal rise time (t_C-H), synchronization signal rise → external clock fall time (t_C-H), and rise slew rate (ts), refer to the electrical specifications section in the relevant data sheet.

(2006/03)

How are the output pins configured?

The output pins have a CMOS configuration, with an output impedance of approximately 100 Ω or less.

(2006/03)

Is it possible to change the background color of a specific area?

It is possible. Since the background color is set at a whole screen, first set the character reverse ON/ OFF command (which is set in screen units; in the uPD6466, this is the character color reverse ON/OFF command) to ON. Then set the reversing control bit (in the uPD6466, this is the character color reverse specification bit) of the displayed character control command (which is set in each character) to ON (see Figure 3-1).

Figure 3-1. Example of Display Using Character Reverse

(2006/03)

If the character display is distorted or if no character is displayed, what adjustments should be made?

Check the following points and make the corresponding adjustments.

1. Is the dot clock oscillating?
An OSD LSI uses the dot clock to write data to video RAM. If dot clock oscillation is stopped, since the data that is supposed to be transferred is not written to video RAM, the characters are not displayed.

2. Are Hsync and Vsync being input?
The timing generator resets the horizontal control section, vertical control section, and output controller by using the Hsync and Vsync signals that are input, and generates reference signals for counting. If Hsync and Vsync are not being input, since the timing generator is not generating reference signals, the characters are not displayed.

3. Is the command continuous input enable time satisfied?
If the command continuous input enable time is not satisfied, the data that is supposed to be transferred is not written to video RAM, and the character display is distorted.
Check the T2 time.
T1 and T2 apply as the command continuous input enable time of the command for writing characters (2-byte continuous command).
The value of T2 differs depending on the mode (display ON/OFF), character size, and dot clock cycle.

Reference materials:
uPD6461, 6462 Data Sheet
p.53 "Timing for Continuous Command Input"

(2006/03)

Can the uPD6467 be used with a progressive video signal, too?

It can support both interlace and non-interlace (it does not distinguish fields).
The dot frequency used may exceed the recommended operating frequency range in the case of double-speed scanning.
(The uPD6467 can theoretically be used at around 15 MHz but evaluate thoroughly for practical use.)

Does the uPD6467 support the 1125HD system?

It does operate but note the following restrictions.

• The dot clock frequency should not exceed the recommended operating range (8 MHz max.)
  The recommended dot frequency is 8 MHz maximum.
  The uPD6467 can theoretically be used at up to approximately 15 MHz, but shipment inspection is conducted at 8 MHz, and the operation is not guaranteed at a frequency higher than this.
  
• Unnaturalness of character (aspect ratio)
  NTSC and PAL differ in structure of scanning lines. If a progressive video signal is output as is, it will look vertically compressed when displayed.
  The uPD6466 and 6467 have a function to set the character size aspect ratio independently (1 to 4 ), and therefore, the vertical size may be adjusted according to the horizontal dot clock.
  

The specifications for the dot configuration of characters have been fixed based on the assumption that ordinary NTSC or PAL (EIA, CCIR) TV signals will be used.
Characters are output in synchronization with Hsync and Vsync input to the uPD6467. Therefore, basically, the operation is not limited by the number of scanning lines.
However, since the 1125HD system differs from a system for which the uPD6467 are intended, thorough previous evaluation is required.