Video-System OSD LSIs (uPD6464A, 6465)

Is a crystal oscillator required?

It is required when 4fsc crystal oscillation is selected by the oscillation method control command. This is because the 4fsc signal generated by the oscillator and VCO is used as the reference clock for synchronization signal generation when the internal video signal mode is set, and the fsc signal generated by dividing this 4fsc signal by four is used as the reference clock for internal video signal generation and for the synchronization separation circuit (when the external video signal mode is set).
Be sure to use the crystal oscillation control command to set crystal oscillation to ON when displaying characters.

(2006/03)

How accurate (close to) 14.31818 MHz should the frequency be?

An accuracy of ±500 Hz is sufficient.
The deviation of the sub-carrier frequency of 3.579545 MHz for broadcasting standard should be approximately ±20 Hz, but for general consumer products, the deviation can be approximately ±100 Hz.
However, the accuracy of the sub-carrier frequency may pose a problem only when internal video signals are used.
In the external video signal mode, the frequency is used only for the clock of the synchronization separator and may deviate in a range of ± several 100 Hz.

An external video signal and characters are displayed overlapped, with only the characters being misaligned and the video signal being normal.

Although the cause cannot be specified without seeing the actual symptom, it appears that there is a problem with the sync signal.
To use the uPD6464A in the external video mode, a composite sync signal synchronous with the video signal must be input from the CSYIN pin (pin 17).
When such a problem occurs, there are two likely causes for the external video signal and character signals misaligning out of synchronization.

(1) There is a problem with the sync signal input to CSYIN.

• Monitor the CSYIN signal to check for abnormalities in level and phase.
  
• Check if noise is superimposed on the CSYIN signal.
  The uPD6464A recognizes a pulse of 0.2 us or more as Hsync.
  Therefore, if a noise pulse of 0.2 us or more is mixed with the CSYNC signal it is recognized as Hsync, causing the vertical position counter to advance.

(2) Sync separation operation cannot be performed inside the uPD6464A.

• To use the uPD6464A in the external video signal mode, a composite video signal input from CSYIN is separated into a horizontal sync signal and a vertical sync signal by the synchronization separator.
  As the clock for separation, a countdown clock from the 4fsc oscillator is used.
  Therefore, if the operation of the 4fsc oscillator is abnormal, the sync separation operation is abnormal.
  If the above problem occurs, check if the 4fsc oscillation is correct.

I input a 1 Vp-p signal for an experiment and it was output as is
Is there any problem if I use the IC as is?

There is a problem.
To make the input signal 1 Vp-p in the external video signal mode, the level of the internal video signal (character signal) must be adjusted accordingly. Perform the following setting.

1. Internal video signal amplitude control bit	VPD = 0
2. Voltage applied to Vcnt pin	2.5 V

Item 1 above can be changed by a command, but item 2 requires modification of the hardware.
The voltage of the pin cannot be changed by a command.

- Forcibly apply 2.5 V to the VCNT pin from an external source.

- Insert a resistor between Vcnt and VDD (+5 V)   to adjust the voltage applied to Vcnt to 2.5 V.

The level of VBSO pin is determined by a voltage-dividing resistor connected between the Vcnt pin and VDD (+5V).
The above two methods may be used to adjust the voltage applied to the Vcnt pin to 2.5 V.

Reference document:
OSD LSIs User's Manual Figure 2-9 in "2.2.3 Video signal output section"

Is fsc input required?

It is required when ×4 multiplication oscillation is selected by the oscillation method control command. This is because the 4fsc signal generated according to the fsc input is used as the reference clock for synchronization signal generation when the internal video signal mode is set, and the fsc signal generated by dividing this 4fsc signal by four is used as the reference clock for internal video signal generation and for the synchronization separation circuit (when the external video signal mode is set).
Be sure to use the crystal oscillation control command to set crystal oscillation to ON when displaying characters.
In the uPD6464A or uPD6465, the on-chip ×4 multiplication oscillation circuit enables the mounting area and cost to be reduced by using an LC oscillator instead of an expensive crystal oscillator.
Also, since the oscillation precision is decreased due to low Q with just the LC oscillator, the stable oscillation at 4fsc is secured by a phase locked loop (PLL) formed by inputting fsc.

(2007/01)

When fsc input is not used, what must be connected with the FSCI pin (pin 9)?

Connect the FSCI pin to GND or VDD and do not leave it open. Also, use the oscillation control command to select 4fsc crystal oscillation.

(2006/03)

When SECAM is not used, what must be connected with the SECAM pin (pin 22)?

If the video signal method control command is used to select an option other than SECAM, the SECAM pin (pin 22) is disconnected from the internal circuits by an internal analog switch. Therefore, it makes no difference whether something (such as GND or VDD) is connected to this pin or it is left open.
However, if something is connected, note the absolute maximum rating of the input pin voltage (VIN: -0.3 to VDD + 0.3 V).

(2006/03)

What must be connected with pins 13 to 18 when they are not used?

Leave them open.

(2006/03)

When only the internal video signal is used in the uPD6464A or uPD6465, must the composite synchronization signal (CSYNC) be input?

The composite synchronization signal (CSYNC) does not need to be input when internal video signal mode is used. With the uPD6464A or uPD6465, the synchronization signal is automatically generated by using the 4fsc signal generated by 4fsc crystal oscillation or ×4 multiplication oscillation.

(2006/03)

What is the scanning method when internal video signal mode is used?

When internal video signal mode is used, the scanning method is "non-interlacing". The number of horizontal scan lines is 263 lines per field for NTSC or PAL-M method and 312 lines per field for PAL or PAL-N method.

(2006/03)

What are the voltage levels of composite synchronization signal (Csync) input to the CSYIN pin (pin 17)?

The CSYIN pin (pin 17) has normal logic input.
Therefore, the input levels are as follows according to CMOS input regulations.

        Input high level voltage: 0.7V_DD (MIN.)
        Input low level voltage: 0.3V_DD (MAX.)

(2006/03)

When the display is set to OFF in the uPD6464A/6465, is the data from VBSI directly output through VBSO?

When the display is OFF in external video signal mode, the data from VBSI is directly output through VBSO.
Also, when the display is OFF in internal video signal mode, a single screen color is displayed using the color specified as the screen background color.

(2006/03)

If the CSYIN pin (pin 17) is high level in external video signal mode, what is the output status of the HSYO pin (pin 15: horizontal synchronization signal output) and the VSYO pin (pin 16: vertical synchronization signal output)?

The HSYO pin and VSYO pin both remain low level.

(2006/03)

If a 2-byte continuous command is transferred at this time, is the data written correctly to video RAM as long as the command continuous input enable time (TB2, TB2') is satisfied?

In transferring a 2-byte continuous command, if the CSYIN pin is fixed to high level, the tHWL of the command continuous input enable time becomes infinitely large, and data cannot be written when the display is ON (because no clock for writing is supplied from the LC oscillation). Therefore, in this situation, data writing to video RAM stops when the display is ON and operates when the display is OFF.

(2006/03)

How much can the VBSO pin (pin 21: composite video signal output) drive?

Since the VBSO pin of the uPD6464A or uPD6465 only outputs the video signal that is input to the VBSI pin (pin 24: composite video signal input) straight through via an analog switch, the VBSO pin does not have sufficient drive capacity. Therefore, an emitter/follower circuit (buffer) consisting of a single transistor must be added to the VBSO pin (pin 20) to drive circuits in the next stage.
See "3.1.1 Sample uPD6464A or uPD6465 application circuits" in the OSD LSIs User's Manual (S13197E) for details.

(2006/03)

What criteria are used to select a varactor diode?

Use a varactor diode whose capacitance changes in the range of approximately 2 to 10 pF when the voltage varies by 1 to 4 V.
Also, since the capacitance of the capacitor connected to pin 12 is the value when 1SV163 is used, be sure to re-evaluate the capacitance of the capacitor when the varactor diode is changed.

(2006/03)

How do the uPD6464 and uPD6464A differ?

The uPD6464A has a PAL-N method in addition to the video signal methods supported by the uPD6464 (NTSC, PAL, PAL-M, and SECAM).

(2006/03)

Is a pull-up resistor required for the PCL pin (pin 7)?

No, a pull-up resistor is not required. The uPD6464A and uPD6465 include an on-chip resistor of approximately 50 kΩ between the PCL pin and VDD.

(2006/03)

If the display is set to ON after a power-ON clear operation is executed and no characters are displayed on the screen even when various types of commands are transferred, what adjustments should be made?

Check the following points and make the corresponding adjustments.

1. Is the dot clock oscillating?
An OSD LSI uses the dot clock to write data to video RAM. If dot clock oscillation is stopped, since the data that is supposed to be transferred is not written to video RAM, the characters are not displayed normally.

2. Is the composite synchronization signal (CSYNC) being input?
In external video signal mode, the uPD6464A/uPD6465 timing generator resets the horizontal control section, vertical control section, and output controller by using the horizontal synchronization signal (Hsync) and vertical synchronization signal (Vsync) obtained by synchronization separation of the composite synchronization signal (CSYNC). It also generates reference signals for counting.
If no composite synchronization signal (CSYNC) is being input, since the timing generator is not generating these reference signals, the characters are not displayed normally.
In internal video signal mode, since Hsync and Vsync are automatically generated within the device, the characters are displayed even if no composite synchronization signal (CSYNC) is being input.

3. Is 4fsc oscillation occurring?
In the uPD6464A and uPD6465, the 4fsc or fsc signal generated by 4fsc crystal oscillation or ×4 multiplication oscillation is used for synchronization separation of the composite synchronization signal (CSYNC) (when external video signal mode is selected) or for generation of the internal video signal and internal synchronization signal (when internal video signal mode is selected).
If no 4fsc oscillation is occurring, since signal separation or generation is not being performed, the characters are not displayed normally.

(2006/03)

What is S₁ of the command continuous input enable time TB1+21/fosc*S₁+T_HWL1 shown in the description of the 2-byte continuous command in the uPD6464A, 6465 Data Sheet?

In relation to the BUSY period of the 2-byte continuous command shown in the data sheet, S₁ of command continuous input enable time TB1+21/fosc*S₁+T_HWL1 and S₂ of 21/fosc*S₂+T_HWL2 indicate the character size, and they are either 1 (time) or 2 (times).

As the recommended operation timing in electrical specifications of the data sheet, the minimum clock cycle (t_TCLK) is stated to be 1 us. Since eight clocks are used, the minimum clock period is 8 us. If the calculation result of TB2 or TB2' is greater than the value of TB1 + (Seven clock cycles (at least 7 us) of CLK input), use the calculation result of TB2 or TB2' as is. If it is less, however, do not use the calculation result of TB2 or TB2' but use the value of TB1 + (Seven clock cycles (at least 7 us) of CLK input).

(2007/04)