All OSD LSIs

Can external clock input be used?

If continuous external clocks are input, there is a risk that the external buffer that supplies the external clock and the transistor, which is inside the device, for forcibly stopping oscillation during the Hsync period may short. Consequently, an abnormal current may flow in this circuit, and the transistor may seriously be damaged. We therefore do not recommend inputting an external clock.
Refer to "3.3 External Clock Forced Input to LC Oscillation Circuit Section" in the OSD LSIs User's Manual (S13197E) for details.
Dot clock LC oscillation or external clock input can be selected by using the mask option for the uPD6461/6462 or the initialization command fn the uPD6466.

(2006/03)

Must serial data be synchronized with Hsync/Vsync?

Serial data and Hsync/Vsync are not synchronized. However, when transferring video RAM write data, the command continuous input enable time must be strictly observed.
After serial data is transferred, if that data is related to video RAM writing, the data is written to video RAM by using the dot clock. The time required to write this data to video RAM when the display is OFF is 12/fosc the character size (in the case of the uPD6461/6462).
The time required for writing the video RAM data when the display is ON is 21/fosc × the character size + tHWL (in the case of the uPD6461/6462), because the dot clock is stopped during the Hsync period and it requires several clocks to resume oscillating.
For details of the command continuous input enable time, refer to the "Timing for Continuous Command Input" section (uPD6461, uPD6462, or uPD6466) or the "BUSY Period for Command Input" section (for uPD6164A or uPD6465) in the relevant product's data sheet.

(2006/03)

In cases when the /PCL pin changes from high level to low level some time after applying power to the OSD (with the /PCL pin connected to VDD and high level when power is applied (i.e., tPCLL is not satisfied)), what happens to the output from applying power to power-ON clear execution?

The output cannot be predicted. tPCLL must be made satisfied. If imaging forcibly, examples are shown as the following.


However, in both these cases, since the external video signal mode display is set to OFF when the /PCL pin falls to the low level, the unexpected character display output is stopped.

(2006/03)

Does the OSD LSI have any kind of internal switch so that no unexpected data is output when the power is applied in the situation described above?

The OSD LSI contains no kind of internal switch.

All NEC OSD LSIs are designed so that the power-ON clear operation is executed simultaneously when the power is applied. Since no unexpected data is output if the power-ON clear operation is executed, we decided that no switch was required.

(2006/03)

How do you decide the LC oscillation constants?

Please refer to "2.1.1 Dot clock oscillation circuit" in the OSD LSIs User's Manual (S13197E).

(2006/03)

What are the differences between initialization by the video RAM batch clear command and that by the power-ON clear operation?

The main difference is that power-ON clear operation resets the IC's internal circuitry (hardware) from the unstable state that occurs when power is applied, whereas the video RAM batch clear command is primarily used to initialize registers, counters or the video RAM which the other commands can set after a power-ON clear operation is executed.
The video RAM batch clear command is also unable to clear the test mode.

(2006/03)

Are fields distinguished?

In NEC Electronics OSD LSIs, fields such as V, ODD, and EVEN are not distinguished.
Display characters are updated internally according to the Hsync timing.

(2006/03)

Is data set in the video RAM maintained as long as a command does not change the data?

Since an OSD LSI has an on-chip refresh timer, video RAM data is maintained unless the power-ON clear operation, video RAM batch clear command, or display character control command is executed, or the power is turned off.

(2006/03)

What is a 2-byte continuous command?

Please refer to the "2-byte continuous command" explanation in the "TRANSFERRING COMMANDS" section of the relevant data sheet.

(2006/03)

Are there any limitations concerning the Hsync and dot clock timing relationship?

As long as the command continuous input enable time is satisfied, there are no specific limitations. For information about the command continuous input enable time, refer to the relevant data sheet.

(2006/03)

In transferring a 2-byte continuous command, why does the command continuous input enable time when the display is ON include the horizontal synchronization signal (Hsync) width?

In an OSD LSI, when the display is ON, every Hsync trigger resets the internal system timing and controls the display position. Since the dot clock is not supplied to the internal circuitry during LC oscillation and the Hsync period due to these operations, no data is written to video RAM.
However, the command is accepted even during the Hsync preiod (because the data input shift register shown in the block diagram in the data sheet dows not use a dot clock) and, therefore, it can be transferred, but observe the command continuous input enable time shown in the data sheet.

(2007/08)

When a PAL signal is input with the same settings for the horizontal/vertical display start positions and dot clock frequency as those used for NTSC signal input, the vertical size of the characters is compressed and a space appears in the lower portion of the display screen (see Figure 1-1). What causes this?

This occurs because the number of scan lines differs in the NTSC and PAL methods, as shown in Figure 1-1.
Therefore, when a PAL signal is input, the horizontal/vertical display start positions and dot clock frequency must be adjusted, and the display area must be moved (the horizontal/vertical display start positions and dot clock frequency are adjusted depending on each video signal method).
Also, since a character nondisplay area is generated consisting of 53 scan lines per frame (equivalent to approximately 1.5 times of the smallest size character) when an NTSC signal is input and 143 scan lines per frame (equivalent to approximately 4 times of the smallest size character) when a PAL signal is input (see Figure 1-2), the same display cannot be output in both signal methods.

(2006/03)

In terms of OSD LSIs, what are NEC standard models?

NEC standard models are products in which a standard character pattern, described in the relevant product's data sheet, is prewritten to the internal ROM instead of being created by the customer.
The ROM codes for the NEC standard models in the OSD lineup are shown below.

uPD6450GT-102
uPD6464AGT-101
uPD6465GT-101
uPD6466GS-001
uPD6467GR-001

(2006/03)

Are the standard character patterns the same for all OSD products?

No, there are small differences in the character patterns. We therefore recommend that you check the relevant product's data sheet.

(2006/03)

Can I create a character pattern and can NEC Electronics write it to the internal ROM for me?

At present, this is only possible with the uPD6467GR.

(2006/03)

A VRAM write command is shown in the item "Command Continuous Input Enable Time" of the data sheet, but such a command is not shown on the command list. What is this command?

The VRAM write command is a general term for commands that write data to VRAM (video RAM) and includes two commands: a video RAM batch clear command and a display character control command. Since a dot clock is used when the data is written to the VRAM, the time required for successively transferring these commands is specified in terms of time of this dot clock. Especially note this specification, because the display character control command is a 2-byte continuous command.

FAQ for reference:2-byte continuous command transfer

(2007/08)