uPD77210 Family

Description:

The system clock is automatically switched to a divided clock when the HALT instruction is executed. If this timing and HALT mode release by interrupt acknowledgment conflict, the HALT mode release signal may not be sampled. As a result, the system clock may stop, which may cause the uPD77210 to deadlock. The uPD77210 runs normally in conditions as shown below: The HALTS pin is set upon execution of the HALT instruction by the DSP. The system clock is switched to a divided clock in response to the signal from the HALTS pin. HALT mode is released by an interrupt generated after the HALTS pin is set. The uPD77210 deadlocks in conditions as shown below: The HALTS pin is set upon execution of the HALT instruction by the DSP. An interrupt signal that has been sampled exists when (1) occurs. Setting the HALTS pin and releasing HALT mode conflict. The signal cycle from the HALTS pin becomes shorter. The HALT mode release signal cannot be sampled by the divider circuit and the uPD77210 deadlocks.

Workaround:

There is no workaround. Make sure that execution of the HALT instruction and HALT mode release by an interrupt do not conflict.

Description:	By just clearing the EN bit of a PMT control register (PMC) to 0, the BM bit of PMC is not set to 1 (transfer not in progress), and the buffering should only be suspended and kept waiting while the transfer is in progress.
Workaround:	To stop PMT transfer, set the ST bit of PMC to 1 (stopping transfer), confirm if the BM bit is 1 (transfer not in progress) and the EN bit is 0 (stopping PMT transfer), and then evaluate if the transfer is complete. In addition, PMT transfer from the internal memory to a peripheral is complete when the last data is transferred to the peripheral. Judge whether or not the last data has been output from the peripheral by using the user program, as necessary.

(Described in uPD77210 Family User's Manual (2nd edition))

Description:	When starting the ASIO operation after the uPD77210 Family has been started, the ASO pin outputs undefined data that is not anticipated. This is because the ASOS register is not initialized immediately after the power is applied and the contents of the register are not defined. Therefore, even if the data to be output is stored in the ADST register, undefined data will be output before LRCLK falls. Undefined data is output both in the master and slave modes.
Workaround:	When using ASO, take appropriate measures, such as muting on a codec side.

Description:	When no store access is performed on the ASDT register during a LRCLK frame while the ASOEN bit of the ASST register = 1 (audio serial output enable) and the ASOQ bit of the HA2R register = 1 (ASO driver drive onNote), the ASO signal does not become Hi-Z. Consequently, data stored in the ASOS register is repeatedly output in synchronization with the fall of LRCLK. Note: uPD77214 only
Workaround:	There is no workaround. However, the latest data stored in the ASOS register is repeatedly output and converted into analog signals by the D/A converter in the next stage, so the analog signals is 0 Hz and can not be listened.

Description:	When performing audio output in master mode, an out-of-sync occurs if the ASOEN bit is not set to 1 at the same time as supplying BCLK/LRCLK (by clearing the MSSEL bit of the ASST register to 0). This is due to the difference between master mode and slave mode in generating the control signal upon parallel-to-serial conversion that is performed in the ASIO register when performing audio output. In master mode, the ASOEN signal latched at the rise of BCLK is used as the control signal. In slave mode, the ASOEN signal latched at the fall of LRCLK is used as the control signal. In master mode, transfer is started by setting the ASOEN bit to 1 regardless of supplying LRCLK, so an out-of-sync occurs if the ASOEN bit is not set to 1 at the same time as supplying BCLK/LRCLK. For the same reason, an out-of-sync occurs when output from the ASO pin is suspended using the ASOEN bit.
Workaround:	When performing audio output in master mode, set the ASOEN bit to 1 at the same time as supplying BCLK/LRCLK (by clearing the MSSEL bit of the ASST register to 0). After that, do not reset the ASST register or control output using the ASOEN bit because these operations could cause an out-of-sync.

Description:	With the reset function of a serial status register, the serial status register initializes flags related to serial I/O and the internal counter, but it does not initialize the I/O shift register. The TSO/ASIO/SIO interrupt in master mode is based on the internal counter, so an out-of-sync may occur upon reset.
Workaround:	Do not use the reset function of the serial status register. There is no problem when resetting the serial status register at the start of the TSIO/ASIO/SIO initialization sequence after hardware reset release.

Description:	Serial interrupts are not generated even if data is stored to or loaded from the TSDT/ASDT/SDT register when the store error flag or load error flag is set (error).
Workaround:	When the store error flag or load error flag of the serial status register is set (error), directly clear the error flag; do not clear it by the reset function (reset enable bit) of the serial status register.

Description:	Even if a signal that does not satisfy the MIN rating value specification (6tcC ns) of the INTmn low-level width described in the data sheet is input to the external interrupt pin due to a factor such as a noise, it might be recognized as an interrupt.
Workaround:	Satisfy the specification described in the interrupt timing requirements in the AC characteristics.

Description:	An erroneous description was found in the uPD77210 Family User's Manual (2nd edition) concerning insertion of access waits via the MWAIT pin. According to the specification, MWAIT (after synchronization) is generated by latching MWAIT twice, not once. To stop the wait counter for 3CLK in the above timing chart, MWAIT must be input as shown below.
Workaround:	Insertion of waits via the MWAIT pin is not possible if the access wait cycle is not set to 3 or longer in the MWAIT register.

After data is stored in the HDT register in a uPD77210 Family device, the HRE pin becomes active low (HRE = 0 (low level)) by being masked (the HREM bit of the HST register = 1) and then unmasked (the HREM bit of the HST register = 0).
When data has not been stored in the HDT register, the HRE pin remains inactive (HRE = 1) even if this sequence is performed. In addition, the HRE pin becomes inactive (HRE = 1) by being unmasked (the HREM bit of the HST register = 0) and then masked (the HREM bit of the HST register = 1), regardless of the HRE pin preceding status.

This is also applicable on the write side. The HWE pin is forcibly made inactive when it is masked using the HWEM bit, and the pin status varies depending on whether or not data has been loaded in the HDT register when masking is released.

When communication with the CPU is performed via HIO in an encode system, in the command transmission, the handshake is performed by polling the HREF pin. In the encoded stream transmission, when the CPU activates DMA and performs handshake by using the HRE pin, if the HRE pin is masked by a DMA transfer completion interrupt before the last data has not been transmitted to the CPU, the last data will never be transmitted.

(Described in uPD77210 Family User's Manual (2nd edition))

The edge at which the clock source is counted varies depending on the setting of the TCLKPS bit in the TCSR register.

• When the prescaler value is 1/1: The count occurs at the falling edge of the timer clock source signal.
• When the prescaler value is other than 1/1: The count occurs at the rising edge of the timer clock source signal.

(Described in uPD77210 Family User's Manual (2nd edition))

When the system clock is switched, a regulating clock that has a longer high-level width than before or after switching is inserted.

(a) External clock → PLL multiplier clock (divided clock → undivided clock)


(b) PLL multiplier clock → external clock (undivided clock → divided clock)

The regulating clock's high level width is as follows.

• When clock is switched from external clock to PLL multiplier clock (or from divided clock to undivided clock):
  (2 × division rate or multiplication rate + 4.5) × undivided clock cycle or PLL multiplied clock cycle
• When clock is switched from PLL multiplier clock to external clock (or from undivided clock to divided clock):
  (8 × division rate or multiplication rate + 1) × undivided clock cycle or PLL multiplied clock cycle

During this period, sampling errors may occur due to the lengthened system clock, so the timer and serial interface should be stopped before switching clocks.

The AC specifications of the peripherals prescribed under the internal system clock must be satisfied, including the regulating clock, if the peripheral is used even while the system clock is switched.

For example, the MIN value of the serial clock (standard serial interface) is rated as "50 and 2 × tcC ns", so 2 cycles of the system clock, including the regulating clock, are required when using a serial interface for switching the system clock. If this specification is not satisfied, an out-of-sync may occur.

When the system clock is switched, a regulating clock ^Note with a high-level width longer than that before or after switching is inserted. Interrupt requests that are acknowledged during this period may not be detected normally. Make sure that no interrupt requests occur when switching the system clock.

Note:

See "Caution on switching system clock (Clock)" for the high-level width to be inserted.

(Described in uPD77210 Family User's Manual (2nd edition))

The switching of the clock source (CLKIN direct, PLL output, or divider output) is performed via the CLKC register. Note with caution that at least 16 instruction cycles are required after switching the settings for the PLL and divider circuits.

(Described in uPD77210 Family User's Manual (2nd edition))

Although the CLKIN direct clock is used as the system clock when reset is active at startup, the following clock is selected in the boot process.

• PLL output clock (except for external memory boot or non-boot)
• CLKIN direct clock (for external memory boot or non-boot)
• Divider: Divider operation (1/1), divider output clock is not selected

When the FINT instruction is executed while the serial data register load enable flag of TSIO, ASIO, or SIO is set (enabled), no subsequent load enable interrupt will be generated.

(Described in uPD77210 Family User's Manual (2nd edition))

• Parallel access cannot be targeted at the peripheral area (0x3800 to 0x3FFF).
• External memory access to the area from 0x8000 to 0xFFFF when DPR = 0x3F is routed via the MIO peripheral, and parallel access is not permitted when it involves a peripheral.
• Since DPR is shared by X and Y memories, simultaneous access to different pages is not possible.

Table 2-9 Conditions for Simultaneous Access to X and Y Memories

X Memory Y Memory		0x0000 to 0x37FF	0x3800 to 0x3FFF	0x4000 to 0x7FFF	0x8000 to 0xFFFF
					DPR = 0x00 to 0x3E	DPR = 0x3F	DPR = 0x80	DPR = 0xC0 to 0xFF
0x0000 to 0x37FF		OK	-	OK	OK	OK	OK	OK
0x3800 to 0x3FFF		-	-	-	-	-	-	-
0x4000 to 0x7FFF		OK	-	OK	OK	OK	OK	OK
0x8000 to 0xFFFF	DPR = 0x00 to 0x3E	OK	-	OK	OK	-	-	-
	DPR = 0x3F	OK	-	OK	-	-	-	-
	DPR = 0x80	OK	-	OK	-	-	OK	-
	DPR = 0xC0 to 0xFF	OK	-	OK	-	-	-	OK

(uPD77213 only)

When the busy signal in the program sequence is judged based on the busy flag of the SDSBR register in the DSP, the busy flag only indicates the busy signal ^(Note1) that is generated after data is written to the SD card.
If this flag is also used for detecting the busy signal ^(Note2) in programming mode after the STOP command (CMD12) is executed when multiple write is complete, the busy signal cannot be detected on the software side. Consequently, the next command may no longer be able to be issued, depending on the software specifications. Care must be taken on the software side when detecting the busy signal.

(Note1)	See Figures 28 and 29 on page 58 in SD Memory Card Specification Part 1 V1.01
(Note2)	See Figures 30 to 33 on pages 59 and 60 in SD Memory Card Specification Part 1 V1.01

(Erroneous omission in uPD77210 Family User's Manual (2nd edition))

The following descriptions are added to the item concerning the change of serial I/O mode in the uPD77210 Family User's Manual (2nd edition).

•Timing of changing serial output mode:

Serial output mode (data length: 8/16 bits, LSB/MSB first, etc.) is determined by the value in the SST register when data is stored in SDT (out). Do not change the SST value when the SSEF bit is 0 (data exists in SDT (out)). Change the SST value when the SSEF bit is 1 (SDT (out) is empty).

•Timing of changing serial input mode:

Do not change the SST value while serial input is being performed. When serial input continuous mode is set (SICM = 1), clear the SICM bit to 0 while the SLEF bit is 1, change the serial input mode (data length: 8/16 bits, LSB/MSB first, etc.) and re-set the SICM bit to 1. The SST value becomes valid from the data input after the two data input to SDT (in) and SIS has been loaded.

When SRTX and SRRX have been set to 111 (slots 112 to 143), can slots 128 to 143 be accessed?

Since a frame supports until 124 slots (frame sync signal can be up to 128 slots), if SRTX and SRRX are set to 111, it is not possible to use slots past the first 128 slots.

I want to access the external memory by program while the external memory is being accessed by the PMT controller in a DMA operation. However, I realize I cannot access the MDT register in this case because this operation will conflict with the PMT operation. Instead, can I use direct access?

Yes, direct access can be executed while PMT controller is accessing the external memory because direct access and PMT access are arbitrated.

In cases when this is possible, if direct access is performed while the PMT controller is executing memory input and output at the same time, which external memory access has priority?

This situation does not occur because the PMT controller is designed so that the access is not performed continuously (it is done intermittently), so if a conflict occurs, the direct access will always be executed when the PMT controller is not performing access.

Conversely, if the PMT controller accesses the memory while direct access by the program is being executed continuously, will the PMT access be held pending? Or are the access rights passed alternately from the program to the PMT controller?

If direct access conflicts with PMT access, the PMT access will be processed first. PMT access is executed intermittently, so the direct (kernel) access operation will be executed between PMT accesses. Therefore, if direct access is executed by program continuously, the access rights are passed alternately between the program (direct access) and the PMT controller.

If access to the internal RAM, which occurs when the PMT controller is transferring data to the external memory, conflicts with continuous access by the program to the same internal bank RAM, is the PMT access held pending until continuous access by the program is completed? Or are the access rights passed alternately from the program to the PMT controller?

As described in the PMT transfer procedure in the uPD77210 User's Manual, if the PMT controller and the program (direct access) attempt to access the same bank at the same time, a wait is inserted in the direct (kernel) access. The program (direct access) access operation is carried out after the PMT transfer is completed and when the PMT controller is no longer executing access.

When booting the external data memory, the program in the DSP's internal ROM for booting first reads the 5-word header section (from the step count to the MSHW settings), sets those values to each register, and then reads from the external data memory to the internal RAM depending on the conditions described in the 5-word header section. On what kind of conditions is this initial header section itself read depending?

In an external data memory boot operation, the settings for reading the boot header (0x8000 to 0x8004) are as follows: DPR register = 0x3F, MIDX register = 0x0000, MWAIT register = 0xFFFF, MSHW register = 0xFFFF. You must therefore write this 5-word boot header to external memory addresses 0x00000 to 0x00004.

(2007/06)

I want to use a reboot to write the initial values to the internal data RAM. In this case, if I set DP2 = 0x0 as the transfer address, am I right in thinking that the data will be written into the internal RAM in order of X:0x0, Y:0x0 even if I don't write to R5L (DPR setting)?

In rebooting, it is also possible to write into the internal data RAM.
For example, written into 0x0000:X memory, 0x0000:Y memory as a boot in the uPD77210, since the same program as the one used to boot the instruction memory is used, data are sent in 32-bit units in the form of a block of the higher 16 bits for Y memory and a block of the lower 16 bits for X memory. The transfer order is the same as when executing a reset boot: lower 16 bits first, higher 16 bits second. It is not possible to transfer to the X memory or Y memory separately in a reboot. Also, since the internal RAM has no relation to page settings, it doesn't matter what value you write to R5L (DRP).

(2007/06)