uPD77111 Family

Is the upper word data transferred to the lower part of the memory address or the higher part?

  SampleX  XROMSEG  INTERNAL
  Samle:   DWL   0x12345678

In this case, the 0x1234 is transferred to the lower part, and 0x5678 is done to higher part.

Regarding development tools, where can starter kits that include the uPD77111x be obtained, if they are sold?

Andor System Support Co., Ltd. 2-15-8 Minami Shinagawa, Shinagawa-ku, Tokyo, Japan Tel: +81-3-3450-8101

While it is not a starter kit, there is a product called "Library Board" from Andor System Support Co., Ltd. For more information about this product, contact the manufacturer.

What is the procedure from power-on to program operation for the uPD77110?

1) First, allocate the vector table for interrupts, etc.

2) If reboot is necessary (programmed from 0x4000 to 0xBFFF), set the host reboot parameters (R7L, DP3) starting from address 0x240,   and execute Call 0x6.
  The program is downloaded from the host interface and allocated to the specified area.

3) Execute the instructions following this instruction (Call 0x6).

For details, refer to CHAPTER 4 BOOT FUNCTION of the uPD77111 Family ArchitectureUser's Manual.

It is possible to stop the clock input to the CLKIN pin in the STOP mode, but after that, when the STOP mode is canceled from the WAKEUP pin, is it necessary to again perform host booting of the instruction RAM via the host interface?

If the stop mode is canceled with the WAKEUP pin, the register and memory contents are retained, so it is not necessary to execute bootup again.
After the stop mode has been canceled, execution restarts from the next instruction after the stop instruction.

Before the stop mode is canceled, check whether the clock is stabilized.
After making sure that the clock is stably supplied, enable the WAKEUP pin for the specified period.

Note that if WAKEUP is executed while the clock is unstable, and the period during which WAKEUP is enabled is short, the internal memory and register contents may be destroyed.

Is it possible to stop the clock input to the CLKIN pin in the STOP mode?

If yes, when canceling the STOP mode with the WAKEUP pin, what is the minimum number of clocks that must be supplied before the WAKEUP signal input?
Are 4 clocks like for the RESET signal at power-on required?

Also, what is the minimum number of clocks that must be supplied before cancellation with the RESET pin (hardware reset)?
Are 4 clocks like at power-on required?

Yes, the clock supply from external can be stopped in the STOP mode.

In this case, the number of clocks required before /WAKEUP input is not prescribed, and any number is fine as long as a stable clock is supplied.

In the case of cancellation with /RESET, the minimum number of clocks can be 4 from the previous reset cancellation.
However, in this case as well, stable clock supply is required.

The DSP and A/D are connected using a serial interface.
The A/D output data length is 20 bits. Can the conversion data be loaded at the timing shown in the following figure?
Which should be used for loading, the blue or black timing?

If SIEN is made "L" at the black timing, 16-bit data can be received.
With 20-bit data, simply making SIEN "L" at the blue timing does not enable all the 20 bits of data to be received. This is because the serial registers in the DSP have a 16-bit configuration and the amount of data that can be handled at one time is therefore 16 bits. 20-bit data can be received by dividing reception into two times via the program and transferring the data from the 16-bit serial registers.



If SIEN is active at the falling edge of SCK of the last (16th) bit of first 16-bit input data, the hardware enables the next 16-bit serial data to be input without pause (continuously) (as indicated by the blue timing of SIEN).
Note that SIEN (or SOEN) in the uPD7711x does not indicate the effective width of the data. SIEN is simply a signal that enables input (or output in the case of SOEN) of the next 16 bits of data. Sampling is performed only in the part immediately before input (in 16-bit I/O mode). Therefore, even if SIEN is made inactive upon the input of the 17th bit, the next 16 bits of data are input.

Similarly, 20-bit data reception is performed as reception of two continuous 16-bit data groups (32 bits of SCK are required). The program transfers data from the serial register to another register or memory immediately after the first 16 bits of data have been received, and then repeats the process immediately after the second 16 bits of data have been received. The first 16 bits of data plus four bits in the second 16 bits of data make up the 20-bit data being handled.

What is the method for calculating the power consumption during operation?

The maximum current is as indicated in the data sheet.
The listed values are guaranteed for 30 ns cycle operation, but can also be estimated as being almost directly proportional to the operating frequency.

Regarding the merit value, the current value can be estimated as approximately 0.5 mA/MHz.
However, the consumption current varies according to the program, so this value is only a rough guide.
The guaranteed value is the maximum value listed in the data sheet.

How much does the consumption current value differ when the clock input to the CLKIN pin in the STOP mode is supplied and when it is stopped?

The value is estimated to be approximately 0.3 uA/MHz in the STOP mode.
For example, when a 20 MHz clock is input, the consumption current value is approximately 0.3 * 20 = 6 uA.

What is the maximum consumption current value for the 3.3 V and 2.5 V units when 8 MHz is input to the CLKIN pin and 40 MHz operation (PLL × 5) is performed?

The guaranteed value is 75 mA (33 MHz, 2.7 V operation) as listed in the date sheet (tester selection criteria at time of shipment).

The actual measurement values using a product on hand at the time are listed below. These measurements were not performed for 40 MHz input (8 MHz x 5). These values should be regarded as rough guidelines.

Moreover, the consumption current is influenced only by the operating clock, and is unaffected by the relationship between the input clock and multiplication factor of PLL.
Therefore, the multiplication factor condition is irrelevant.

Actual measurement values are listed below for reference purposes. (These are not guaranteed values.)

Consumption current values of IVDD unit of uPD77110 to uPD77114   • Operating voltage: IVDD = 2.5 V   • Operating frequency: 33 MHz (16.5 MHz input, x2 multiplication factor)   Consumption current during normal operation:     Typ. value: 15.5 mA (Nominal value: Approx. 0.5 mA/MHz @ 2.5 V)     Max. value: 34.2 mA (Approx. 1 mA/MHz)       The Typ. value is estimated from actual measurement during execution of PSI CELP program.       The Max. value is the actual measurement value during execution of a program for current selection at time of shipment.     When IVDD is changed from 2.5 V to 2.7 V, the consumption current value increases by as much as 15% based on actual measurement.     When the operating frequency is changed from 33 MHz to 40 MHz, the consumption current value increases by as much as 20% on a calculated basis.

Consumption current values for EVDD unit of upD77110 to uPD77114   • CLKOUT output mode   • 10 MHz toggle operation   • I/O power supply voltage: 3.0 V   • Pin load capacitance: 10 pF   Consumption current of CLKOUT pin per 10 MHz toggle:     2.6 mA/pin The above are values obtained when only the CLKOUT pin is operated, performing CLKOUT pin output. The consumption current value is largely proportional up to approximately 30 MHz toggle. For the consumption current per toggle, the value above can be divided by 10M. Regarding the consumption current per swing, further division by 2 is acceptable. Calculation for all the I/O pins yields the EVDD consumption current.

In programming using the uPD7711x, if
  #define DATA 0b1111111111110000
is defined, and
  r0 = r0 & ~DATA
is described in the program, is the R0 register ANDed with "0Fh"?
(Is the ~DATA notation allowed?)
Also, where are such coding rules listed?

This notation is possible, but restrictions apply.
If MSB of the result of the calculation with a certain name defined by #define or EQU as 16-bit data becomes 1, the assembler (WB77016) may output an error message "evaluation out of range".
In order to avoid the error, define it as 32-bit data.

I plan to use uPD77110 for development, but to use the uPD77112 (mask ROM) for the product.
Is the setting of P0 = P1 = 0 OK? Also, what is the application startup method at this time?

If performing host boot of the program code to the instruction RAM of the uPD77112, P0 = 1 and P1 = 0 are used.
Moreover, if all the programs are described in mask ROM (uPD77112 standalone operation), self boot is used, so P0 = 1 and P1 = 1 are used.

After bootup, the operation is started from address 0x200 according to the instruction code.
In commercialization, the reboot entry program described in the uPD77110 becomes unnecessary.

I want to perform DMA transfer from the host side during data transfer at host boot and host reboot, but does the ROM in the DSP support these boots?
Also, what kind of operation does program on the ROM in the DSP perform?

The boot sequence is described in the following document.

Reference document:
uPD77111 Family Architecture User's Manual - CHAPTER 4 BOOT FUNCTION

Program on boot ROM writes the data transferred by using this sequence to the instruction area. The sequence is shown below. The respective transfers (HOST → DSP) are performed by twice 8-bit transferring, the lower 8-bit first, then the higher 8-bit.

Host boot

  (Host → DSP) Dummy data transfer
  (DSP internal) Data pickup from HDT
  (Host → DSP) Transfer of boot instruction count 
  (DSP internal) Data pickup from HDT (Here, instruction count = n) 
  (Host → DSP) Transfer of HST setting value 
  (DSP internal) Data pickup from HDT and writing to HST 
                 The HAWE bit is set to 1
                 regardless of the HST setting value from the host.

The subsequent sequence from here is the same as that of host reboot.
Before performing host reboot, the boot instruction count (here, "n") and HST (HAWE bit = 1) must be set.

  (Host → DSP) Transfer of 1st instruction code (lower 16 bits)
  (DSP internal) Pickup of data (instruction code) from HDT,
                 transfer to instruction area 
  (Host → DSP) Transfer of 1st instruction code (higher 16 bits)
  (DSP internal) Pickup of data (instruction code) from HDT,
                 transfer to instruction area 
  (Host → DSP) Transfer of 2nd instruction code (lower 16 bits)
  (DSP internal) Pickup of data (instruction code) from HDT,
                 transfer to instruction area 
  (Host → DSP) Transfer of 2nd instruction code (higher 16 bits) 
  (DSP internal) Pickup of data (instruction code) from HDT,
                 transfer to instruction area 
  (Host → DSP) Transfer of 1st instruction code (lower 16 bits) 

                         :

  (Host → DSP) Transfer of nth instruction code (lower 16 bits)
  (DSP internal) Pickup of data (instruction code) from HDT,
                 transfer to instruction area 
  (Host → DSP) Transfer of nth instruction code (higher 16 bits)
  (DSP internal) Pickup of data (instruction code) from HDT,
                 transfer to instruction area 

                         :

   End of boot routine  
     Host boot: Branching to address 0x200  
     Host reboot: Branching to next instruction of reboot routine call 

The DSP internal is at the wait status as long as 16 bits of data have not been input to HDT.
In this state, the DSP does not perform other types of processing and solely waits for data input from the host.

The HWE pin and HWEF (flag in HST) are provided to indicate whether the DSP is in a state to pick up the next data, as viewed from external (host, DMA controller).
So, you should perform transfer while monitoring the state of this pin from external or while polling the HST register.

Only instruction code transfer is supported for boot and reboot.
If initialization of the data RAM area is required, it is necessary to transfer data from external by the program that has been booted.

Please describe the host boot procedure.

The procedure is as follows. (For further details, refer to CHAPTER 4 of the uPD77111 Family Architecture User's Manual .)


<Transfer Contents>

The area that can be booted by host boot at reset is 0x200 to 0xFFF.
Regarding booting of the area from 0x4000, reboot is executed by the program in the DSP.

Note: Reset

After power-on, secure reset input H level for 4 input clock cycles before setting L (active). Then secure it L level for 100 us + 2048 input clock cycles or more before setting H (inactive). This is in order to set PLL lockup and the PLL multiplication factor. For reset after power-on, 4 system clocks or more is OK as long as the PLL multiplication factor is not set again. Note that if a reset width of 1024 system clocks or more is inserted, PLL initialization (re-setting) gets executed. If PLL has been initialized, bootup is required. (For details, refer to 4.2 Initializing PLL in the data sheet.

I want to eliminate external ROM by writing the program of the DSP (uPD77110GC) along with the program of the microcontroller to the internal flash ROM of the microcontroller (uPD78F4216A).

In case that the program for the DSP is written in the external ROM of the microcontroller and is loaded from the microcontroller to the DSP, the DSP operates normally.

The HEX file output by the workbench for the DSP starts from address 0000, but what is the method for starting this from the address (1D000h) of the flash ROM in the microcontroller?

Since this is not possible with the DSP workbench, perform the following operation with the microcontroller tools.

Join two objects by downloading the program of the uPD78F4216A and further downloading the HEX file of the DSP by setting an offset with the 78K4 debugger.

Save the joined object program as a new HEX file and use that to program the flash ROM.

What is the concrete operation procedure with the DSP workbench in order to place the program of the DSP from address 1D000h of the 78K4?

This processing cannot be performed with the workbench of the DSP. Perform this processing with the tool of the 78K4.
  (1) First, start up the simulator or the debugger of the 78K4.
  (2) Download the program of the 78K4 in the usual manner to regular addresses.
  (3) Next, select [Download] in [File] in order to download the HEX file of the DSP. A dialog box for downloading will appear.
  (4) Find the [offset value] parameter of [option] in the dialog box that is set to 00000, and change it to 1D000.
  (5) Deselect the symbol check box.
  (6) Change the file name extension to [*.HEX].
  (7) Select the HEX file of the DSP.
  (8) Click the [OK] button to start downloading.
The HEX file of the DSP can be downloaded to addresses from 1D000 using the above procedure.

This question concerns the external data memory access time specification of uPD77110.

In the External Data memory Access - Switching characteristics table under 10. ELECTRICAL SPECIFICATION of the data sheet, the MWR low-level width is specified as "tcC x tcDW - 3 (ns)." What should be assigned to tcDW for 0-wait (no wait) operation?

External memory cannot be accessed with no wait. Since access with a value of 0 is not possible, specify a wait value of 1 or higher.

In the uPD77110, I think, the instructions in the bootup ROM area of 0000 to 00FF writes data from external to the internal instruction RAM area, but in the case of host boot and host reboot, writing to RAM is described as being done via the host interface.

Regarding the host interface, the only address pins is HA0/1, and the method how to connect with external memory is unknown. Please provide a reference circuit, if available.

Bootup is not possible using only external memory.
Data are transfered from the memory connected to the host processor or DMA controller, via the host interface.

For a circuit configuration example, see Figure 4-2 Configuration Example of Host Boot System in the uPD7701x Family Architecture User's Manual.

Regarding the X/Y memory, does the DSP have two spaces from 0000 to FFFF?

Yes, this way of looking at it is fine.