Host Controllers

What is a USB 2.0 host controller?

A host controller controls all the connected USB devices.
The control method is defined in the USB standard, and a USB 2.0 host controller controls all USB devices by satisfying the entire USB 2.0 standard.

What is the relationship between the host controller and driver?

The host controller controls USB devices, but that control method follows a set of rules determined by the software.
In other words, its operation could be described as reading a procedure manual provided by the software, operating accordingly, and then supplying the results as feedback to the procedure manual.

The software that manages the procedure manual is the device driver.
Without the driver, the host controller cannot function.

What are OHCI and EHCI?

The rules set between the host controller and the driver is the Host Controller Interface (HCI).

OHCI (Open Host Controller Interface) is defined in the USB 1.1 host standard. Another interface besides OHCI is UHCI.
EHCI (Enhanced Host Controller Interface) is a standard that was created by Intel as the USB 2.0 standard was being drafted.

The host controllers of NEC Electronics comply with OHCI and EHCI.

What are the specifications of the USB 2.0 host controllers of NEC Electronics?

Up to five USB ports are provided.
Each port can be connected to USB devices of different speeds, i.e. HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps).

Furthermore, our USB 2.0 host controllers also provide one EHCI host controller core and two OHCI host controller cores.
On the system side, a PCI bus (PCI 2.2 standard compliant) is provided, allowing direct connection to the PCI bus.

What are the features of the USB 2.0 host controllers of NEC Electronics?

The uPD720100A was the world's first USB 2.0 host controller. At the time of its release, the only USB 2.0 host controller that existed was the uPD720100A, so that Microsoft used that product when developing drivers for Windows XP.
Other embedded OS vendors also used it as their driver development environment platform.

Furthermore, the uPD720100A having gained broad adoption in the market, there are many cases of peripheral manufacturers using NEC Electronics' host controller for evaluation purposes, and it has gained a reputation as a standard host controller that is the most unlikely to cause problems.

Moreover, it offers lower power consumption, high transfer capacity, and a smaller package compared to competing products.

Why are two OHCI host controller cores provided?

The host controller controls USB devices that are connected to it.
When a large number of USB devices are connected, the bandwidth available to each device is limited.

When, for example, a camera and speakers are connected, dropped frames of the camera or breaks in the sound of the speakers may occur.
Taking bandwidth into consideration, this problem can be remedied by connecting each device to its own host controller.

In the case of the OHCI interface for controlling conventional low-speed (12 Mbps) devices, consideration of the bandwidth is particularly important, and thus NEC Electronics' host controllers feature two OHCI host controller cores.

Concretely, ports 1, 3, and 5 are controlled by the OHCI1 host controller core, and ports 2 and 4 are controlled by the OHCI2 host controller core.

How are EHCI and OHCI switched?

NEC Electronics' host controller automatically detects the transfer speed of the connected devices.
Prior to USB device connection, EHCI is the owner of each port. When a USB device is connected, the transfer speed of the connected device is automatically detected in the sequence laid out in the USB 2.0 standard.

The uPD720100A notifies the system about whether the connected device is an HS or FS/LS device, and if it is a FS/LS device, it switches over to OHCI (actually, this control is performed jointly with the driver).
In other words, the uPD720100A checks the connected device. If the connected device is an HS device (FS/LS device), EHCI (OHCI) becomes the owner of the port in question.

How are 30 MHz oscillation operation and 48 MHz clock input operation switched?

The specifications differ according to the host controller, as follows.

	30 MHz oscillation	48 MHz clock input
uPD720100A	CLKSEL pin = L	CLKSEL pin = H
uPD720101	Clock_sel bit = 0	Clock_sel bit = 1

Clock_sel bit: Bit 5 of EXT2 register

Can the 48 MHz resonator be used for the system clock?

No. In the case of 48 MHz operation, clock input from an external oscillator is required.

Can a 30 MHz ceramic resonator be used for the system clock?

No. An accuracy of ±500 ppm is required for the input clock.
NEC Electronics recommends the use of a resonator with an accuracy of ±100 ppm, and ceramic resonators are basically not recommended.

How should unused pins be connected?

Please connect pins as follows.

DPx/DMx	: Fix to low level
RSDPx/RSDMx	: Leave open (unconnected)
PPONx	: Leave open (unconnected) (pin for Vbus control connected to power switch, etc.)
OCIx	: Fix to high level

Is there a problem if the INTA, INTB, and INTC pins are connected together?

These pins can be connected together without problem, but since the value of the interrupt pin of the PCI configuration space that indicates the destination of interrupt requests for OHCI1, OHCI2, and EHCI is fixed, it cannot be changed.
This must be considered on the system side.

How is the CRUN0 pin used?

This pin is defined in PCI Mobile Design Guide Version 1.1. It is mainly used to control on/off switching of the PCI clock in mobile PCs, etc.
When not using this function, fix it to low level.

How is the LEGC pin used?

This pin is used when a USB keyboard/mouse is emulated to a PS2 keyboard/mouse for desktop PCs, etc.
When this function is not used, the LEGC pin is not used, so please fix it to Low level.

Why does the 9.1 kΩ resistor connected to the RREF pin have to have an accuracy of ±1%?

The RREF pin, along with the AVSS(R) pin, is used to generate the reference voltage of the internal analog circuit. In order to raise this accuracy, the connected resistor must have an accuracy of ±1%.

Moreover, regarding the board design, care must be exercised about the layout so that these pins are not affected by noise.
For details, refer to the USB 2.0 Board Layout Guide (to register as a user, click here.)

Why does the 36 Ω resistor connected to the RSDP/RSDM pin have to have an accuracy of ±1%?

In the USB 2.0 standard, the DP/DM pins are terminated with 45 Ω ±10%.
Since the host controller of NEC Electronics complies with this standard with regard to the total of the internal resistance of the RSDP/RSDM pins and the 36 Ω external resistance, an accuracy of ±1% is required.

If the accuracy of this resistance value is low or if a different value is used, this may have an influence on the USB waveform.

Is serial ROM required?

If the system software that is used can write to the EXT register of the PCI configuration space, serial ROM is not required.
In this case, the SRMOD, SRCLK, and SRDTA pins can be left open (unconnected).
However, in the case of a system such as PCI card or PC card that cannot be set from system software (BIOS), serial ROM is mandatory.

Is a power switch mandatory?

This depends on the system. Per the USB 2.0 specs, overcurrent must be detected and reported to the system, but the way this should be implemented is not specified.
One possible approach is to use a PolyFuse design that does without a power switch.

Please note that polarity of power switches differs among manufacturers and that care should be exercised during selection.

Does AVDD have to be separated from VDD?

AVDD is the power supply for the internal analog circuit. Therefore, to reduce the noise of the AVDD as much as possible, it is necessary to separate it from the regular VDD.

What should one be careful about with regard to the board layout?

Please refer to the USB 2.0 Board Layout Guide (to register as a user, click here.) Particular care is required for noise countermeasures, etc., for the wiring in the area around the analog circuit and the differential signals of the USB.

How does the uPD720101 differ from the uPD720100A?

The basic circuit of the uPD720101 is equivalent to that of the uPD720100A. While inheriting its stability, it features low power consumption, and supports small package (reduction in power consumption of approx. 35%, 12 x 12 mm FPBGA package), which are requirements for applications such as notebook computers.

Moreover, it complies with Rev. 1.0 of the EHCI standard and boasts an increase of approximately 20% in transfer speed.

Can the number of ports be changed?

Yes, between 2 and 5 ports can be specified with bits 2:0 of the EXT1 register

Which is the setting for not performing port power supply control?

Set bit 21 of the EXT1 register to "0".

Which is the setting for not using EHCI?

EHCI can be masked by setting bit 0 of the EXT2 register to "1". In this case, all the ports are controlled by the OHCI host controller core, and even HS devices are perceived as FS devices.