IEBus Interface (uPD6708, uPD72042, uPD72042B)

How is IRQ (interrupt) detected?

IRQ is detected either of the following two ways.
(1)Hardware: By connecting the IRQ pin to the INT pin of the host CPU.
(2)Software: By detecting IRQ (flag of FLG register) via polling.

Note, however, that in the case of (2), if the communication rate is fast or the amount of data to be communicated is large, IRQ detection may be missed. We therefore recommend using method (1).

What causes IRQ (interrupt) to be generated?

IRQ is generated when the following occur.
(1)The LSI runs away. (At this time, the RAW flag of the FLG register is 1.)
(2)The return code of the RCR register changes.
The return code indicates a state at the start or at the end of the communication when the unit is communicating as the master or a slave.

Please tell me about the microprogram crash flag (watchdog timer).

The microprogram crash flag is a flag that starts up the watchdog timer to prevent the microprogram that executes the internal communication processing in the uPD72042 or uPD72042B from entering an infinite program loop (crash) while an instruction is stopped, waiting for data on the IEBus to arrive.

<Microprogram flow>


Loop A is exited when data arrives, or when the data cannot be received and an error occurs.
The microprogram crash flag will not be activated by an external trigger since the watchdog timer (WDT) value is set to a value larger than the maximum time of loop A.
It is assumed that a microprogram crash occurs when something causes a malfunction of the LSI's internal hardware or microprogram.
The microprogram crash flag may also be activated by the timer value being undefined when the timer is started without a reset being activated after power is supplied.

When transmission is stopped after a master has received NAK, how is this recognized on the host side?

In normal communication, if a slave has not received data correctly, it returns NAK to the master. This NAK is sent at the end of the slave address field, control field, telegraph length field, or data field.
If the master receives NAK and transmission stops, that communication is aborted halfway and the return code changes.
At this time, the host is notified by the generation of IRQ.

If a command is written to the CMR register during communication, how long a wait is required until that command is executed?

When a command is written to the CMR register during communication, the register is overwritten, but the command execution will be put on hold until the end of the current communication.
Therefore, a wait of up to 1 frame is required until command execution. For example, the wait of 15.2 ms is required in the case of mode 1.

Can it be OK to request to enter standby mode during communication?

Even if a request is made to enter standby mode during communication, standby mode cannot be entered unless communication is completed and the system is in the carrier sense state.
Also, if a request is made to enter standby mode during communication, internal registers are banned to be read via serial I/O until the LSI actually enters standby mode.
Therefore, you should not requesting to enter standby mode during communication.

Can I connect elements with self-inductance such as a noise filter to the bus line?

If elements with self-inductance are connected to the bus line, communication errors may occur due to the occurrence of timing errors.
We therefore advise you not to connect elements with self-inductance such as a noise filter to the bus line.

What points should I note when using the uPD6708 and uPD72042B together?

The uPD72042B is designed to allow for an external protection resistor, whereas the uPD6708 is not.
Therefore, when using the uPD6708 and uPD72042B together, use the following recommended protection resistance and terminating resistance values.

• Terminating resistor: 120 Ω (dual ended) or 60 Ω (single ended)
• Protection resistor for uPD72042B: 180 Ω
• Protection resistor for uPD6708: 0 Ω

I have never had a problem with receiving data of about 10 bytes; however, a reception error occurred this time when I tried to receive 26 bytes.
The error is a data field ACK error and seems to have occurred at the 21st byte.

The size of the read data buffer in the uPD6708 is only 20 bytes, so the interrupt request which shows the buffer full is generated when the 20th byte of data has been received.
At this time, unless the data in the buffer is read within the specified time, the 21st byte of data cannot be received into the buffer, causing slave reception to abort halfway without ACK being returned.

To fix this problem, it is necessary to read the data in the buffer within the specified time (about 390 us) once the interrupt request has been generated.
Note that at this time, if only one byte of data is read, the interrupt request will be generated again when the 21st byte of data is received.

Can the IEBus bus line be monitored using the uPD6708, uPD72042, or uPD72042B?

No, it cannot.

Section 6.1 in the uPD72042B Data Sheet contains a list of "Communication Flags". What are these?

These are the communication flags (defined as arguments or global variables) used in the main and interrupt routines shown as a sample of microcomputer processing flows used to control the uPD72042B, which appear in chapter 6 of the data sheet. The flag names in the table are given by way of example only.

In the uPD72042B Data Sheet, it says that if the communication speed is 6 MHz and the mode is set to Mode 1, the execution transfer rate will be 17 kbps. Does this just refer to the transfer rate of the data bits in the data field (i.e., the actual data)?

No; this value refers to the transfer rate of all the bits, including the header, parity, and acknowledge bits.
In Mode 1, it takes 410 us to transfer one byte of a data field (which includes the parity and acknowledge bits).

(2006/07)

Input high voltage/input low voltage and common mode input voltage, high/low voltage are shown in the IEBus driver/receiver characteristics of electrical specifications of the data sheet. How do they differ?

The input high voltage/input low voltage defines a potential difference (voltage) between the BUS+ and BUS- pins. If this difference is 120 mV or more, the high level is recognized; if it is 20 mV or less, the low level is recognized.
On the other hand, the common mode input voltage, high/low voltage defines a potential difference (voltage) between BUS+ and ground or between BUS- and ground. In order to be recognized as the high level, BUS+ and BUS- must be at 1.0 V to V_DD - 1.0 V and the potential difference between BUS+ and BUS- must be 120 mV or more. In order to be recognized as the low level, BUS+ and BUS- must be at 0 V to V_DD and the potential difference between BUS+ and BUS- must be 20 mV or less.

(2007/08)

What is the relationship between high level/low level on IEbus and logic 0/1?

The low level on the IEbus (difference in potential between bus lines (BUS+ pin and BUS- pin) is 20 mV or lower) is equivalent to logic 1, and high level on the IEbus (difference in potential between bus lines (BUS+ pin and BUS- pin) is 120 mV or higher) is equivalent to logic 0.

(2007/11)