uPD98431 (10/100 Ethernet Controller)

Section "3.9.3 Transmitting pause control frame" in the User's Manual has the following about the transmit timing of pause control frames: "when the quantity of data in the receive FIFO exceeds the threshold level set by the RFDMH field."

Is the timing for subsequent retransmission the time when this condition is again met after the amount of data in the receive FIFO has become lower than the value (zero frame transmission level) indicated in the RFDML field?

When data uploading from the receive FIFO of the MAC is stopped on ground of the higher-level device, is it possible to make the MAC execute retransmission automatically/manually?
Are there transmission instructions and a periodic transmission function for pause control frames?

The uPD98431 does not have function to execute pause control frame transmission automatically and periodically.
Moreover, the uPD98431 does not support function for directly triggering automatic generation and automatic transmission from the higher side.
Pause control frames are automatically generated and transmitted only when passing each threshold level.

To perform flow control in relation to link partners, pause frames are input from the FPGA to the uPD98431. Can the uPD98431 output these input pause frames directly to the link partners?
[FPGA → uPD98431 → Link partner]

Output is possible. Frame transmission can be performed in the same way as normal transmission operation by writing pause control frames from the higher-level FPGA to the transmit FIFO.

However, since the operation is done as normal frame transmission, care must be exercised regarding counters.
For example, since TXPF (pause control frame transmission counter) is designed specification-wise to count using the pause control frame automatic transmission function in the uPD98431, it does not count in this case.

This question regards aborting transmission. If a packet with a length exceeding the maximum packet length (set by the LMAX register) (hereafter, referred to as oversized packet) is transmitted, is the data from the start bit until the maximum packet length transmitted, and once transmission of the portion up to the maximum packet length has been completed, does transmit abort occur?
(Are abnormal packets (without CRC) transmitted to a PHY device?)

Yes, that is correct. Since transmission stops when LMAX exceeded is detected, the packet contents are transmitted from the beginning up to abort, even in the case of transmission to PHY.

This question regards the PTVR register (pause timer value read register). What is the order of the pause timer value?
Also, is the pause timer value of pause frames transmitted from the MAC side the same order?

The pause timer counter unit defined in the IEEE standard corresponds to 1 unit of this register. Concretely, it is 512-bit time.
This unit is also applied to the pause timer value set by the MACC3 register.

This question regards back pressure. If packet reception is detected a number of times while this function is enabled, will dummy packet transmission and forcible collision generation occur each time packet reception is detected?

The back pressure operation takes place only when reception is detected while this function is enabled. To enable the back pressure function, the BACKPE bit of the MACC3 register must be 1 and the amount of data in the receive FIFO must exceed the RFDMH value set in the RFIC1 register.

The User's Manual states that in the case of connection to a PHY device manufactured by Broadcom, data is not correctly written to the PHY register. Does this mean that connection is not possible?

This problem can be remedied with software.
The PHY chip in question requires 65 clocks for write access completion.
In this regard, the uPD98431 outputs only 64 clocks, and it is this discrepancy that causes the problem.
Write access can be completed by executing dummy reads following write access to generate clocks to compensate for the insufficient number of clocks.
Please check with Broadcom for the validity of this workaround.

How long is the mirror port I/O delay time?

This delay time, which depends on the clock deviation of the internal synchronization circuit, is in the range of 0 to 8 clocks.

Is it possible to perform continuous read during FIFO bus read by sectioning receive frames at the desired length?

Yes, this can be done by breaking the read operation with the SKIP signal. When the read operation is broken, the uPD98431 outputs 0000B to the RXFDQ pin, causing the state to change to the idle state. If readable receive data does not exist in other ports, the PASS signal is input and receive data read is resumed.
For details, refer to section 3.7.1 (2) (b) SKIP signal in the User's Manual.

Even if the RXFEN# signal is disabled, data read from the receive FIFO does not stop and the subsequent data is read and discarded. The RXFEN# signal is used for chip selection when connecting multiple uPD98431

Can frames without a length value like the following be transmitted and received?
DA(6) + SA(6) + type(2) + data(+pad)(46-1508) + FCS(4)

The uPD98431 can both transmit and receive IEEE802.3 frames (length) and Ethernet frames (type), but is not provided with settings or modes for identifying such frames.
Therefore, frames are not discarded due to differences in the length/type fields.
However, the operation of the bit/statistics counters of the following registers varies depending on whether or not length field check is performed.

TSVREG1 register: TFLOR/TFLER bit
RSVREG register: RLOR/RLER bit
RFLR counter

(There are no error statistics and alarms caused by the transmission and reception of Ethernet frames.)

Moreover, the length/type fields of IEEE802.3 frames include code to control special operations (control frame, VLAN frame), so avoid such type code when using Ethernet frames.