uPD98412 (X.15)

If a bus fight (during several ns) occurs for signals AD31 to AD00, can this destroy the uPD98412 device?

It will likely not lead to destruction, but design must naturally be performed so that bus fights do not occur.
Since performing design that ensures that bus fights will not occur is common sense, please perform your design so that no bus fights occur for this IC.

Are the HTT & control memory and the cell buffer memory of the uPD98412 (ATM switch (X15)) used at the same time?
Also, approximately what memory capacity should be set?

Yes, these memories are used simultaneously.
The HTT & control memory is used as the header conversion table and the working area (control memory) for X15.

The cell buffer memory is used as a shared memory when replacing cells.
The memory capacity is determined according to the number of channels (= number of connections) that should be supported.
Please refer to section "3.12 Header Translation" in the User's Manual.

I plan to connect the uPD98412 to the uPD98404. When used in the 8-bit 12PHY polling mode, the TXADDR and RXADDR signals of the uPD98412 and the uPD98404 are both 4 bits and 5 bits, respectively.
How should I handle address lines of the uPD98404 that are not used? Also, would the handling be the same when the uPD98412 is connected to the uPD98411?

When connecting the uPD98404 and uPD98412, pull up the higher address lines of the unused TXADDR and RXADDR.
In the case of connection to GND, the uPD98412 becomes unable to generate unassigned address 1FH during polling.

The GND connection processing described in the uPD98404 Data Sheet assumes that the uPD98404 is used in the single port mode and that no address lines are used.

When using in the multi-PHY mode, pull up unused address lines.
Also pull up unused address lines when the uPD98412 and the uPD98411 are connected.