uPD98411 (ATM Quad SONET Framer)

0001:	Register access
0002:	Error detection
0003:	LOP detection

D98411 -0001	Register access

Q1	This question concerns section "4.3 Management Interface" in the User's Manual. In the BMODE0 mode (Motorola compatible), how long is the time from after the DS_B signal is made low level until the ACK_B signal becomes active (low)?
A1	The interval of time from after DS_B (RD_B) becomes low level until the uPD98411 makes RDY_B (ACK_B) low level differs depending on the register that is accessed. Please load the data in MD [7:0] after checking that RDY_B (ACK_B) has become low level. The interval of time from after DS_B (RD_B) becomes low level until the uPD98411 makes RDY_B (ACK_B) low level is [4.5 x REFCLK cycle (approx. 235 ns)] max. To make it possible to perform read from any register without using the RDY_B (ACK_B) signal, make the pulse width of DS_B (RD_B) at least [4.5 x REFCLK cycle]. Also, the DS_B (RD_B) recovery time is approximately 364 ns which corresponds to 7 cycles of the REFCLK clock. Do not perform access to the registers at intervals shorter than 7 cycles.
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		(2005/08)

D98411 -0002	Error detection

Q1	I want to obtain the transmission path error rate, but how should I go about it? Is the transmission path error rate related to the B2 error counter register (B2ECT)?
A1	The transmission path error rate is obtained from the BIP errors (B1, B2, B3) detected in receive frames. For example, the B2 error counter (B2ECT) counts up the number of B2 errors (1 to 24) detected per 1 frame reception. Since this counter is cleared to 0 every time it is read, the number of errors detected from the previous read until the current read can be obtained. The error rate is the ratio of the number of bits received during the read interval and the number of errors obtained from the counter.
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		(2005/08)

D98411 -0003	LOP detection

Must the fact that the Path-AIS bit is "0" be made a condition for judgment of alarm cause register (ACR) LOP?
(For the uPD98404, the manual states that this must be included in the conditions, but the uPD98414's manual says nothing in this regard.)

The pointer value detection circuit of the uPD98411 does not simultaneously detect LOP and P-AIS.
However, the display register displays the event logs, and retains "1" for the bits that correspond to the occurred events until it is read.

For example, if LOP is detected, LOP continues to be displayed until the display register is read.
Then, when the pointer detection circuit cancels LOP and P-AIS is detected, both the LOP and P-AIS bits are displayed by the display register.


  
     
    Display register 
     
  
  
    Event
    LOP Detection
    Read
    LOP Cancellation
     P-AIS Detection
  
  
    ----------
    --------
    -------
    -------
    -------
    -------
    -------
    -------
    -------
    -------
    -------
    -----
  
  
    LOP bit 
    1 
    → 
    0 
    → 
    → 
    → 
    → 
    → 
    → 
    → 
      
  
  
    P-AIS bit 
    0 
    → 
    → 
    → 
    → 
    → 
    → 
    → 
    1 
    → 
      
  


However, if LOP is not read, results in below, and when the display
register is read following P-AIS detection, it appears as if both
LOP and P-AIS are detected.


  
    Event
    LOP Detection
    Read
    LOP Cancellation
     P-AIS Detection
  
  
    ----------
    --------
    -------
    -------
    -------
    -------
    -------
    -------
    -------
    -------
    -------
    -----
  
  
    LOP bit 
    1 
    → 
    → 
    → 
    → 
    → 
    → 
    → 
    → 
    → 
      
  
  
    P-AIS bit 
    0 
    → 
    → 
    → 
    → 
    → 
    → 
    → 
    1 
    →

If both the LOP and P-AIS bits are set to "1" when the display register is read the first time, it is known that there has been a LOP → P-AIS or P-AIS → LOP transition in the past, but which is the current state is not known.

And if either the LOP or P-AIS bit is set to "1" when the display register is read again (second time), the current state (in other words, the transition direction) can be known because only the bit corresponding to the event that has occurred subsequently is set to "1" at this time.
If both the LOP and P-AIS bits are "0" when the display register is read the second time, this means that the event has already ended though which transition occurred is not known.

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		(2005/08)

uPD98411 (ATM Quad SONET Framer)

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