uPD98410 (X.10)

Is there a setting method so that polling control is not performed?

No, there is not.
Polling is performed even in the single PHY mode.

To what extent do malfunctions occur when logical ports not connected to PHY are open?

Malfunctions may occur with one polling operation in the worst case. The extent of malfunctions depends on various factors.

Are ports polled individually of each other?

With regard to X10 and X15, polling is individually performed between UTOPIA ports.

This question is about the minimum threshold value register for the total cell count.
Does the value to be set have to be the value obtained with the equation described on the User's Manual?

No, it does not have to be exactly the value obtained with the equation, but please set a value that is close to that value.

If the value to be set is greater than the one obtained with the equation, do malfunctions occur even if the total cell count does not exceed the setting equation value?

Please refer to A1 above.

When changing the value of the EN bit of the port configuration register, is it necessary to stop the switch operation and change the value of the total cell count minimum threshold value register?

No, neither is necessary when changing the value of the EN bit.
In the initial settings, add in advance the cell count corresponding to the logical ports for which EN may be enabled, and write the value to the total cell count minimum threshold value register before the switch operation is enabled.

For example, the manual states that when the input cells are set as VPI = 0 and VCI = 30H, access to HTT is performed with VPI = 0 and VCI = 20H in order to judge the VP connection and VC connection.
At this time, if the CEN bit of HTT for VPI = 0 and VCI = 20H indicates disabled, I assume that HTT for VPI = 0 and VCI = 30H is referenced as the VC connection, but is this correct?

No, it is not. When the CEN bit of HTT for VPI = 0 and VCI = 20H indicates disabled, the connection is recognized neither as a VP connection nor as a VC connection and HTT for VPI = 0 and VCI = 30H is not referenced. The input cells are discarded as a result.

Stated in a different way, when VPI = 0 and VCI = 30H are set for the VC connection, is it absolutely necessary to enable the CEN bit for VPI = 0 and VCI = 20H to set the switching mode SM bit to VC connection?

Yes, that is correct.
Be sure to enable the CEN bit for VPI = 0 and VCI = 20H to set the switching mode SM bit to VC connection even when VPI = 0 and VCI = 30H have been set for the VC connection.

(1) When cells accumulate in X10 or in the buffer, and the connection is changed from single-cast to multi-cast, I believe that the cells accumulated in the cell buffer may be discarded. In the worst case, are all the accumulated cells discarded?
What is the ratio of cells that are discarded?

(2) When cells accumulate in X10 or in the buffer, and the number of multi-casts is changed, I believe that the cells accumulated in the buffer may be discarded. In the worst case, are all the accumulated cells discarded?
What is the ratio of cells that are discarded?

For both (1) and (2), when cells accumulate in X10 or in the buffer, updating the multiple-addressing output port (MB) of area B in the HTT memory results in a 100% mismatch.

The uPD98410 has four ports for the UTOPIA lv2 interface, but can the clock rate supplied to each port be changed individually for each port?
Example:
  UCLK 0 25 MHz
  UCLK 1 25 MHz
  UCLK 2 25 MHz
  UCLK 3 40 MHz

Yes, the clock rate supplied to each port can be changed individually for each port.

Are there ATM switch LSIs with a wider band than X10?

Yes. The uPD98412 is available.

This question concerns changing the HTT settings of the uPD98410. My understanding is that, in the case of single cast connection, no problems such as skipped cells occur even when the output port is changed without stopping cell switching (while cells are accumulated in the uPD98410 or the cell buffer), but what about short cells?
 * Short cell: Abnormal cell whose size is less than 53 bytes

In the case of the single-cast connection, changing the output port without stopping cell switching (while cells are accumulated in the uPD98410 or the cell buffer) does not cause short cells to occur.

Do short cells not occur even when the connection is changed from single-cast connection to multi-cast connection without stopping cell switching (while cells are accumulated in the uPD98410 or the cell buffer)?

Changing the connection from single-cast connection to multi-cast connection without stopping cell switching (while cells are accumulated in the uPD98410 or the cell buffer) does not cause short cells to occur.

Please tell me about how the registers of the uPD98410 are used. Data is transferred at 64 Kbps to 155 Mbps to the uPD98410 (NEASCOT-X10) with 1 VCI. If correct information is set to HTT, is it possible to transfer data at any transfer rate to the uPD98410 (NEASCOT-X10) without performing special settings?

Yes, that is correct.

Memory access is performed in 16-bit units in the 16-bit access mode for the X10, but is parity error detection for the HTT/CTL memory performed in 32-bit units?
Or is it performed in 16-bit unit?
Looking at the actual machine, it appears to be performed in 32-bit units.

In the 16-bit access mode for the uPD98410 (X10), memory access is performed in 16-bit units, but HTT/CTL memory parity error detection is performed in 32-bit units.

When SPR = 3 is set while this device is used in the continuous output mode and multi-PHY mode with the SWCLK = 33 MHz and UCLK = 25 MHz setting, is the throughput 79.5 Mbps after shaping?

The data sheet states that peak rate shaping does not work at the transfer speed of the UTOPIA interface. Does this mean that the transfer speed of the UTOPIA interface is a rate that is unfailingly lower than 79.5 Mbps?

The throughput after shaping is 79.5 Mbps.
If UCLK = 25 MHz, the maximum transfer rate of UTOPIA is 25 MHz * 8 bits = 200 Mbps.
Since 79.5 Mbps < 200 Mbps, 79.5 Mbps throughput transmission and reception are possible.

Does the UTOPIA interface transfer speed after shaping differ when the continuous output mode is used and not used, even if the same SPR value is set?
Is it correct to assume that in the case of the non- continuous mode, the transfer speed falls to 1/3 or less of 79.5 Mbps?

The UTOPIA interface transfer speed after shaping differs for when the continuous output mode is used and not used, when the same SPR value has been set and the same conditions as those indicated for Q1 are used.

•In the continuous output mode, the transfer speed remains 79.5 Mbps.
•In the non-continuous output mode, since UTOPIA max. throughput 200 Mbps x 1/3 = 66.7 Mbps, smaller than 79.5 Mbps.
 Since the transfer speed is limited by a smaller value, it becomes 66.7 Mbps as a result.

Is it correct to assume that the transfer throughput after shaping is the maximum transfer speed for 1PHY?

The transfer throughput after shaping for a given 1PHY is:
(1) the functionally maximum value for the specific PHY (155 Mbps in the case of OC-3)
(2) the calculated transfer throughput (bps) / (SPR + 1)
(3) the maximum transfer rate (continuous output mode) of UTOPIA or 1/3 of the maximum transfer speed (non-continuous output mode)

Of the above three values, the slowest (smallest) value is the actual transfer throughput after shaping for 1PHY.

What is the capacity of the internal I/O buffers (I/O FIFOs)?

In the X10 (uDP98410), it is 4 cells for both the input FIFO and the output FIFO.
In the X15 (uPD98412), it is 4 cells for both the input FIFO and the output FIFO for the 8-bit UTOPIA, and 8 cells for both the input FIFO and the output FIFO in the case of the 16-bit UTOPIA.

When multi-cast is used with X10, if one of the output destination ports does not respond to polling, the subsequent multi-cast cells are not output for all ports?

For example, if multi-cast is set to output ports 0, 1, and 2, and upon input of cells A + B + C (3 cells), only port 0 fails to respond to polling, the following happens.
  •Cell output is not performed to the output port 0.
  •Three cells, A + B + C, are output to the output ports 1 and 2.
However, cell output starts after port 0 responds to polling.

Under the above conditions, are the single-cast cells to be output to ports 1 and 2 actually output?

Yes, single-cast cells are output to ports 1 and 2.

If the memory mode register is set to HM = 1, is HEC check performed?

HEC check is not performed when the memory mode register is set to HM = 1.

In the X10, if during cell transmission, the path on which transmission is currently being performed is disconnected once (by setting CEN to 0) and then connected again, are the cells accumulated in the cell buffer discarded?
Or are the accumulated cells transmitted when the path is reconnected?

In this case, the cells accumulated in the cell buffer are not discarded.

The cell discard counter is not incremented even though cell discard display is performed in the X10.

If the UB field or OM field of CTENTH (threshold value exceeded discard cell count enable register) is set to "1", counting is executed.

I use the same value for all of OQthUBR, OQthUEP, OQthUCI, and OQthUCL, but is this OK?

It should be fine as long as there is no problem on the system specifications.