uPD98404 (ATM SONET Framer)

In the case of a single PHY octet level handshake, is it necessary to perform assembly into a cell configuration?
Or is transfer performed in the order of 8-bit parallel data input?

Single PHY octet level handshake is a mode in which cell data transfer between a device on the higher ATM control side and the uPD98404 is performed 1 byte at a time.
Transfer can be performed when the byte data of some of the cell data is prepared (refer to transmit side transfer timing chart in the User's Manual).

If the higher side ATM control device has not prepared the byte data, transfer control is performed in byte units, by setting the TENBL_B signal to high and then making it low when byte data is transferred.

The uPD98404 loads data to the FIFO only when the TENBL_B signal is low.
The data to be transferred is in the 53-byte cell format. When 53 byte data is accumulated in the FIFO, the uPD98404 forms this data as a frame and outputs it to the line.

When 8-bit parallel signals occur in real time, to transfer them in real time, is the data transfer speed, omitting the time for overhead and STS-3 POH, 155.53 Mbps x (260/270) = 149.76 Mbps?
If the data transfer speed is a value smaller than this, idle signals are added, but if the data transfer speed is a greater value, is the data discarded?

If data in excess of 149.76 Mbps is input from the cell interface, the transmit FIFOs of the uPD98404 become full for 7 cells, and the uPD98404 notifies this by making the FULL_B signal low.

If the FULL_B signal has become low, the device on the higher ATM control side must stop data input by setting the TENBL_B signal to high within 4-clock cycles.
If data is input regardless of the fact that the FULL_B signal is low, that data is ignored (discarded).

If some available space occurs in the transmit FIFO and the FULL_B signal becomes high again, cell data input can be resumed by making the TENBL_B signal low.

I want to synchronize the uPD98404's transmit frames with the reference clock (8 kHz) from external, but how can I do that?
How is TFSS (transmit frame output disable signal) used?
When the state changes to transmit disable, does frame transmission stop after transmission of the frame currently being transmitted ends?

No. When TFSS is set to high, the uPD98404 fixes the transmit data to either "1" or "0", so the frame currently being transmitted is interrupted. The next time TFSS is made low, the frame is always output from the beginning.

Are transmit frames synchronized just by inputting to TFSS an 8 kHz pulse sampled in an external circuit with the TCL clock?

It is likely to be difficult to always perform synchronization control of the output timing of transmit frames using TFSS.

The uPD98404 transmits frames in synchronization with 155.52 MHz generated using the reference clock (19.44 MHz of REFCLK input pin) of the transmit PLL as the source.
Have you tried inputting the 19.44 MHz clock obtained by multiplying the 8 kHz reference clock to be used for synchronization to the REFCLK pin?
If you do not need to always perform synchronization to 8 kHz, the reference clock of the transmit PLL can be switched to the TFC pin input through register setting mode switching.

However, even if you switch the mode, it is necessary to input the 19.44 MHz clock to the REFCLK pin as the system clock, and since this means changing the transmission clock source the instant the mode is switched, the transmit data is destroyed.

I am concerned about the possibility of the routing of the PECL signal pattern becoming somewhat complicated if I introduce a cheap LED module as the optical transceiver connected to the uPD98404 by simply making some changes among the components mounted on the same board.

Since the data lines between the uPD98404 and the optical transceiver have an influence on the jitter characteristics of transmit and receive data, it is recommended to keep the wiring as short as possible.
Please request layout diagram of the NEC Electronics' evaluation board as pattern routing reference from the distributor.

Please note that evaluation boards being designed simply for evaluation purposes, their operation is not guaranteed, so they should be used for reference only.

How are the error count value set to the B2ECT (B2 error counter) register and the bit error rate (BER) related?

One to 24 B2 errors are detected in 1 frame.
The B2ECT register adds up the detection error count for each frame and stores the cumulative count of detected errors from the preceding read until the current read.
The bit count of one STM-1 frame is as follows.

  270byte x 9raw x 8bit=19440bit(125us)

Let's consider how the bit error rate (BER) is obtained using the receive bit stream count as the denominator and the error bit count as the numerator.
For example, if the counter value is read every 26 frames (26 x 125 us = 3250 us (505440 bits)) and is "5", BER = 10^-5 or lower.

  (5 / 505440) = 0.989 x 10^-5 < 1 x 10^-5 < (6 / 505440) = 1.187 x 10^-5 (bit)

Are there conditions for B2 error detection?

First, for B2 error detection, no mask must be set with PCMR (performance cause mask register) (D3: B2E = 0).
The next condition is that frame synchronization must have been established.
If frame synchronization is not established (OOF: out-of-frame status) and the B2 byte position cannot be detected, a B2 error is not detected and therefore the D3: B2E bit of PCR (performance cause register) is not set to "1".

Are there any product that incorporates the UTOPIA master transceiver interface and can directly interface with 8-bit parallel data of the uPD98404?

The uPD98404 being a product that stores ATM cell data in SONET frames, data must be input in the ATM cell format.
The function to convert the data to be transferred to an ATM cell is performed by a product that incorporates the SAR function.

NEC Electronics offers the following SAR devices:

uPD98405: PCI function + SAR function + PHY function
uPD98409: PCI function + SAR function

Data is loaded via the PCI interface (32-bit bus) to both devices, cells are generated, and they are output from the UTOPIA bus based on the UTOPIA Level 1 interface.
Since the uPD98404 supports both UTOPIA Level 1 and Level 2, it can be directly connected to these SAR devices.

However, if the UTOPIA interface is based on Level 2, there is unfortunately no product that can generate and output cells from an 8-bit wide bus.

Comparing the description of overhead among the physical conditions described in an NTT technical document and the frame format contents of the uPD98404, I have noticed that the Z0, Z1, Z2, Z3, Z4 and Z5 codes differ in the SOH and LOH.
Do these differences cause problems for actual connections?

Regarding the relevant part of the transmit frame overhead, the uPD98404 outputs it fixed to 00H.
The uPD98404 ignores the same byte part in receive frames.

Regarding application to target specifications, carefully study this matter referring to the User's Manual.