uPD98401A (Local ATM SAR)

Is there a queue for accumulating indications in the SAR chip as a stage preceding the transmit/receive mailboxes?

The uPD98401A has a DMA command FIFO that internally accumulates transmit/receive indication contents along with DMA addresses, etc., as DMA command.

If there are queues for accumulating indications in the SAR chip, is there one queue for each one of the four transmit/receive mailboxes?
Or is there only one queue shared among the four transmit/receive mailboxes?

There are two DMA command FIFOs, one for transmission and one for reception.
One queue is used in common for the two mailboxes for reception indications.

However, there is one internal DMA controller for executing commands, and DMA commands are executed in sequence starting from the DMA command that was first output.

When the receive mailbox is queued and the FIFO status in SAR is FIFO full, are transmit indications notified?

No, they are not notified.
The DMA controller in the uPD98401A executes commands in the order in which they are taken from the transmit/receive DMA command FIFO.

When execution of a transfer command for the receive indication that is in first stage is attempted while the mailbox is full, that command is not executed until free space occurs.
Later transmit indications are pended.
If there are DMA commands for later transmit indications, they too are pended.

If the batch addresses stored in the receive indication do not use batches, is 0 stored?

In the case of a packet start address (batch address) in a receive indication when batches are not used, either 0 or the same batch address as the previous indication is stored.
In the case of a receive indication with a packet size of 0, ignore the packet start address.

How many octets is the FIFO size?

The size of the DMA command FIFO is 16 words for both transmission and reception.
One transmission indication is stored using 1 word, and one receive indication is stored using 4 words.

If the PSM bit of GMR is set to 1, is it alright to judge whether or not a batch is used by the length field?

Please judge this with the packet size of the receive indication.
If no batch is used, the packet size stored as 0.

In the uPD98401A, it seems that 32 KVC max. are supported, but what is the maximum number of simultaneous connections that is supported?

In the uPD98401A and uPD98405, 32 KVC max. are supported, and 32 K connections can be set simultaneously.
However, since 32 KVC are shared between transmission and reception, when using 1 connection for both transmission and reception, a maximum of 16 K connections are supported.

Moreover, since transmit/receive VC are set in the control memory area and there are other used areas in the control memory besides transmit/receive VC, the number of connections that is actually supported is less than 16 K (15 K or more).
For details, refer to "5.2 Setting the Control Memory " in the uPD98405 User's Manual.

When using the unassigned cell generator function, the following shaper priorities are set.
In this case, during cell transmission with shaper 0, is this cell transmitted with priority over unassigned cells?

       Shaper priority
   Shaper 0  0000
   Shaper 1  0001  ← Unassigned cell. Specify to generator

Since shapers with a smaller number are processed with higher priority, the data cell of shaper 0 is transmitted with higher priority over the unassigned cell of shaper 1.