uPD72002 (MPSC)

According to the manual, when HUNT is executed during COP operation, comparison with the SYNC character is performed for the purpose of synchronization each time 1 byte is received in the internal sync mode, but how long does this comparison require?

Since SYNC character comparison is performed by hardware, synchronization is established at the time when the SYNC character is input to the receive shift register.

From the perspective of the RxD pin, there are 2-bit delay from the RxD pin to the receive shift register, so the SYNC/HUNT bit becomes "1" at the D1 reception time of the receive data after the SYNC character.

If the first SYNC character is input after receive enable, the state changes from the Enter Hunt state to the SYNC state, and the value of the SYNC/HUNT bit changes from "1" to "0", so that an E/S interrupt cause occurs due to this change.

The DMA controller I am currently using is built into the CPU, and since no DACK (DMA acknowledge) pin is provided, I pull up the DAKTx and DAKRx pins of the uPD72002-11.

In this case, if the operation has actually transferred to DMA operation, must (CS, WR, RD, S/M, and C/D pins) control be performed similarly to regular access to the Tx and Rx buffers?

Yes, that is correct. If there is no DACK pin on the DMAC side, control the CS, RD, WR, S/M, and C/D pins for data transfer like for regular access to the transmit/receive buffers.