uPD72001 (MPSC)

The manual says that in the case of the X1 mode, it is necessary to achieve synchronization externally.
How is this done?

The X1 mode is not per se linked to asynchronous operation.
This is simply common sense derived from asynchronous communication theory.
Moreover, since X1 is synchronous mode communication, receive data and clock must be synchronized.

The manual has been prepared for readers with general knowledge about communication.
For the difference between asynchronous and synchronous communication, please refer to the existing literature (books, etc.).

I use the uPD72001 communication IC in the X1 mode, but get parity errors and framing errors.
These errors disappear when I drop the baud rate to 9600 bps, but I cannot identify the cause.

If X1 is used during asynchronous operation, it is necessary to achieve synchronization externally.

Under your usage conditions, the received data and the reception clock are not synchronized, so normal sampling of receive data is not possible and therefore receive errors frequently occur.
Set the clock rate to X16 or higher.

In the asynchronous mode, I want to enable FirstTxINT of the CR1:D2 bits to perform all transmissions with transmission interrupts, but the user's manual says that an interrupt occurs at the first TxEnable following reset.

When a TxBufferEmpty interrupt occurs at the 1st TxEnable and TxDisable is selected once, do TxBufferEmpty interrupts occur also at the 2nd and subsequent TxEnable?

TxBufferEmpty is a bit that indicates whether or not there is transmit data in the transmit buffer, and when this bit is set, this is interpreted to mean that there is an interrupt cause, and a transmit interrupt request is output.
The state of this bit is not affected by the transmit enable state.

Therefore, after an interrupt (First TxINT/DMA Enable state) occurs at the 1st transmit enable, the transmit data is written, and then when this transmit data is transmitted and the state becomes Empty again, an interrupt occurs because of the Empty state, regardless of the transmit enable state.

If data transmission is performed continuously using one stop bit on the transmitting side and two stop bits on the receiving side, a framing error (stop bit = 0) does not occur on the receiving side, but why is that?
Is it OK if only a 1-bit length is checked for the stop bit during reception by the uPD72001?

Yes, that is correct.
This is because, during asynchronous operation, there is no problem if only 1 bit is checked for the stop bit.
The bit after the last data bit (the parity bit in the case of parity enable) is recognized as the stop bit.

If the value of this bit is 0, a framing error is judged to have happened, and it is "1", normal reception is judged to have occurred.
There is no setting for two stop bits on the receiving side.

I use the uPD72001 with the following conditions: Protocol channel A: BOP, channel B: unused, communication speed: 512 kbps, host interface: DMA, and CPU: SH1.

After checking 1:eof of SR0 D7 (end of frame) in the receive interrupt, I checked whether SR0 D0 (Rx Data Available) is 0: Not Available, in order to check whether the last reception buffer is empty, but it was 1: Available. What conditions apply?

Based on the fact that the DMAC count was (transmitting side transmit data count - 1), it appears that the higher host does not process DRQRxA requests for EOF data.
Check the DMAC processing of the higher host.
By the way, an interrupt of the Special Rx Condition cause and the DRQRx request are output almost simultaneously for EOF.

If the following settings are performed, is TxINT Pending of SR4 set?

BOP mode

Transmit/receive mode via DMA

The transmit/receive interrupt cause bits of SR4A are equivalent to the TxBufferEmpty and RxDataAvailable bits, and TxINT Pending is set.

When Abort and ALL SENT are specified as the source of an E/S interrupt, if an E/S interrupt occurs due to abort and then the ALL SENT bit changes from "0" to "1" before Reset E/S Bit Latch is issued, does an E/S interrupt occur again due to ALL SENT after Reset E/S Bit Latch is issued?

Yes.

If, after checking 1:eof of SR0 D7 (end of Frame) in the receive interrupt, SR0 D0 (Rx Data Available) is 1: Available, is there a maximum of 3 valid data (1-frame data) in the RX buffer of MPSC?

No.
Rx Data Available serves to notify whether or not there is receive data in the last stage of the receive FIFO, and there is no function for notifying whether there is data in the last 2 stages in this LSI.

If the purport of this question is whether, when there is data in the last stage, there is also received data below this, the answer is yes.
Since the FIFO method is used, while the receive shift register is operating, the received data is transferred to the FIFO, and the data is accumulated through the FIFO operation.

By the way, note that if the receive interrupt mode is the First Rx INT mode, the FIFO operation is no resumed if no Error Reset command is output during Special Rx Condition interrupt processing.

If CH.A and CH.B are used in the BOP mode, is it possible to use transmission with DMA and reception with interrupts?

Using the Both CH DMA mode, this is possible if receive interrupts are set to All Rx INT-2.

If, using Both CH DMA mode, receive interrupts are set to All Rx INT-2, do the DRQRxA signal and DRQRxB signal always stay inactive?
Or is a DMA request output?

Similarly to the regular DMA mode, these signals become High when Rx Available is set to "1", and these signals become Low when the host CPU or DMAC reads the receive data.

When performing initialization with NRZI of BOP and executing testing so as to return the signal through connection, I can obtain the expected operation, but when I perform initialization with FM0, no receive interrupt and no receive end interrupt is returned.

The BOP setting has been made but the setting itself looks like it is 44h and asynchronous operation.
During asynchronous operation, neither NRZI nor FM can be used.

In the DPLL mode, when the start flag is 1 byte, reception is not possible. Why?

If the idle state is a flag, synchronization has been obtained beforehand, but if the idle state is a mark, synchronization is obtained upon flag reception.
Therefore, in the case of a flag consisting only of 1 byte, synchronization cannot be secured if the first bit is dropped.

Since flag detection is done with 1 byte, in the case of a 2-byte flag, reception is possible if synchronization is secured during the 1st byte.

I use the uPD72001 in the BOP mode. I would like to use the DPLL output for the clock for transmission and reception, but the manual says that the DPLL circuit function is to generate a clock synchronized with the serial data input to the RxD pin.
Does this mean that when data is not received, DPLL output is not performed? (Data transmission is not possible?)

Yes, this is correct.
The operation of the DPLL circuit is to correct the count value of the DPLL counter, looking at the change edge of the RxD pin state from H to L and L to H, and the DPLL clock is not generated until the Enter Search command is output and the first edge is found.

Moreover, as described on the same page, after the first edge is found, the count value is corrected according to the edge position.
This is a correction of the count value, and if there is not a single change point, naturally no correction can be performed and the clock is generated as is as X32.

In the case of the FM mode, in the case of 2-clock missing, in other words if not a single edge is detected during the interval while the count value is incremented by 32, the Enter Search state is automatically entered, and no DPLL clock is generated until when an edge is found.

Moreover, it goes without saying that during the interval during which no DPLL clock is generated, this clock cannot be used as the transmission clock.
Thus it is a matter of common sense that the DPLL clock is not used as the transmission clock (though this is functionally possible in this LSI).

The reason why is that the DPLL clock changes owing to circuit jitter, and if this clock is used as the transmission clock, the effect of the jitter is doubled when the remote station uses the DPLL.
Therefore, it is common sense to use a clean clock as the transmission clock within the local station.

In No. 243 of the Q&A section of Appendix C of the uPD72001-11 User's Manual, it says that if the E/S interrupt processing is held pending for a long time because there are other higher priority interrupts, it may not be possible to latch the ALL SENT bit.
How long exactly is a "long time"?

The contents of the E/S bits held internally do not change unless the Reset E/S bit Latch command is output.
Therefore, when a given bit is changed and a latch or E/S interrupt cause occurs, and the E/S interrupt processing for that cause is not completed, no E/S interrupt is output until the Reset E/S bit Latch command is output, regardless of how the E/S bit changes and how many times it changes.

With regard to the All Sent bit referred to in the question, the value of the bit changes from "0" to "1" following transmission of the end flag and the E/S interrupt cause occurs, but if generation of an E/S interrupt through the All Sent cause is desired next, the Reset E/S Bit Latch command must be output before the value of the All Sent bit changes from "1" to "0".

In other words, the E/S interrupt caused by the All Sent interrupt of the current frame must be received during the interval from when the end flag of the current frame is transmitted until before CRC transmission of the next frame, and the processing must be completed before CRC transmission of the next frame.

However, E/S interrupts have a lower priority than transmit and receive interrupts, and if the processing performance of the higher host is low, it is likely that only high-priority interrupts will get processed, and that E/S interrupts will not be processed.
In such a case, either the mode must be set to the DMA transfer mode, or the processing power of the CPU must be increased.

As indicated above, the latch operation of E/S interrupts can be predicted based on a good understanding.

When 2 bytes are written to the transmit buffer, which holds 3 bytes of data, what is the length of time until the start bit of the 1st byte is output from the pin?

Your basic approach to this question is incorrect. The transmit buffer consists of one stage.
(The receive buffer consists of 3 bytes.)
If transmit data is written while the shift register is empty, transmission starts after a delay of time corresponding to 3 bit maximum.

However, if transmit data remains in the shift register, transmission starts only after transmission of this remaining data is completed, so the time from when the transmit data is written until the transmit data is output cannot be simply determined.

If, in a state other than TXEMPTY, data is written, is the written data output normally?
Also, does an interrupt occur subsequently?
Is there the possibility of a problem occurring?

In the case of TXFULL, I believe a transmit interrupt is caused by TXEMPTY because the data written later is output and, following data output, the transmit buffer becomes empty. Is there a problem with this way of looking at it?

No, it is fine.
In the TxBuffer Full state, in other words in the state where transmit data has already been written, further overwriting results, and when the shift register becomes empty, the transmit data written at that time is transmitted.

By the way, in the case of the usage method you described, the first data is written ignoring the first TxBuffer Empty with First Tx INT/DMA Enable.
The First Tx INT/DMA Disable function itself inherits the specification of the uPD7201A, the previous product series, whereby the first transmit Buffer Empty, which should normally be detected as an interrupt cause, is not detected as an interrupt cause.
Enabling of this bit serves to make this TxBuffer Empty an interrupt cause as a new function of the uPD72001.

In other words, the state is TxBuffer Empty from the start, regardless of whether this bit is on or off, so that data is correctly transmitted even if this transmit data was not written through an interrupt.
Moreover, the interrupt function is equivalent to skipping of the INTAK sequence, with the only difference that there is no on/off switching of internal interrupt service latch, and the fact that TxBuffer Empty interrupt cause is cleared by the first transmit data write operation, so that there is no problem in particular.

However, a point requiring caution is the fact that in the case of First Tx INT/DMA Enable, TxBuffer Empty is detected after transmission has been enabled, so that operation that makes INT low or DMARQ high is performed, and when the CPU writes transmit data, INT becomes high or DMARQ becomes low.
If the circuit is configured so as to detect these signal changes with an external circuit, etc., caution is required as this may cause erroneous operation due to these signals.

I perform software reset without performing hardware reset, but transmission and reception are not possible.

At power-on, hardware reset (RESET input) is required.
If hardware reset is not performed, software reset (Channel Reset) itself is not guaranteed.
Software reset is a command for performing initialization during normal operation.

Even though I perform hardware reset, transmission and reception are not performed normally.

The state changes to the standby state as the result of hardware reset.
One possibility is that the standby release command (CR0 = 00H) has not been output.

What are the differences between the uPD72001GC-11-3B6 and the uPD72001-8A-3B6? Since the uPD72001GC-11-3B6 is no longer produced, I am thinking of replacing it with the uPD72001-8A-3B6.

Since these two products use different power supply voltages, replacing one with the other is not possible.
Please note that all the uPD72001 products has been discontinued.
The main differences between these two products are listed below.

	uPD72001-11	uPD72001-8A
Power supply voltage	5V	3.3V
System clock frequency (max.)	11MHz	8MHz
Max. transfer rate	2.2Mbps	1.6Mbps

The package surface temperature was found to exceed 100°C based on temperature evaluation.
The ambient temperature is 55°C. I would like to find out whether this is a normal range, so could you tell me the thermal resistance of the package?

This information is not available for this product. The thermal resistances of products with equivalent packages are listed below for your reference.

uPD72001-11	52 QFP	20°C/W
	52 QFJ	10°C/W
uPD72002-11	44 QFP	30°C/W
	44 QFJ	12°C/W
	40 DIP	30°C/W

This product is no longer produced, but we would like to reproduce a set we formerly used to produce, so please indicate a substitute product.

No substitute is available.
In Japan, the following company supplies MPSC modules with subset functions. Contact them for details.

Techno Create, Inc.

http://www.techno-create.com/ (Japanese only)

(2006/11)