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Volume 78 (Sep 09, 2008)
Summary of NEC Electronics Papers Presented at the 2008 Symposia VLSI Technology and Circuits (1/5)
The "2008 Symposia on VLSI Technology and Circuits"—widely recognized as premiere conferences for presenting research results on the latest device, process, and circuit-related developments—were held this year at the Hilton Hawaiian Village Hotel in Hawaii, from June 17 to 20. Here we introduce the papers presented by NEC Electronics or in collaboration with NEC Corporation.
VLSI Symposia Overview
The VLSI Symposia, along with the International Electron Devices Meeting (IEDM) and the International Solid-State Circuits Conference (ISSCC), are premier conferences devoted to semiconductor technology. The VLSI Symposia consist of two separate events: the VLSI Technology Symposium that focuses on device and process-related themes, and the VLSI Circuit Symposium that focuses on circuit-related themes. Prior to the technical sessions, the Symposia also included three one-day short course lectures: "Outlook for 32-nanometer (nm) to 22-nm generation" at the VLSI Technology Symposium and "Mixed Memory Design" and "Power Management" at the VLSI Circuits Symposium.
Papers Presented by NEC Electronics
Seven papers from NEC Group were selected for presentation at the two symposia: four for the VLSI Technology Symposium and three for the VLSI Circuits Symposium.
NEC Electronics researchers were engaged in four of the above: one solely by NEC Electronics researchers, and three in collaboration with researchers from NEC Corporation.
[ Symposium on VLSI Technology ]
- Session 5.3 (collaboration with NEC Corporation)
- Single-metal/single-dielectric gate stack that realizes triple effective work function for embedded memory application
- Nickel disilicide (NiSi2) works well in silicon processes, and for this reason, we succeeded in implementing transistors that have three different threshold values on the same wafer by using NiSi2 as the material for a metal gate. This is one more step forward in the progress toward higher performance and lower cost for system LSI chips that combine DRAM, SRAM and other types of memory.
- Session 11.1 (collaboration with NEC Corporation)
- A New Low-k/Cu Dual Damascene (DD) Direct Contact for Low-loss (LL) CMOS Device Platforms
- We developed a new structure of scaled-down CMOS devices, of which Cu dual damascene (DD) direct contacts are made in reliable low-dielectric-constant (k) films of Silica-Carbon Composite (SCC, k=3.1)) and organo-siloxane (SiOCH, k=3.1).
- Session 16.2
- Reduction of Vth Variation by Work Function Optimization for 45 and 40 nm Node SRAM Cell
- We developed a technique for reducing variation in the characteristics of transistors in LSI chips by using hafnium in the gate insulation layer. This widens the design margin and makes possible the design of 45- and 40-nanometer (nm) SRAM, which has previously been thought difficult.
[ Symposium on VLSI Circuits ]
- Session 7.2 (collaboration with NEC Corporation)
- A Small-Delay Defect Detection Technique That Increases Reliability of LSIs
- A newly developed testing technique enables logic circuit delays in chips and test patterns to be measured quickly, and the small delay defects often missed by conventional screening techniques to be detected, thus enabling us to increase reliability of our LSI chips.
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