Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.
Volume 75 (Feb 27, 2008)
NaviEngine® Multicore Platform and its role in the evolution of car navigation systems: The world's first (*1) system LSI chip for car navigation systems to be equipped with SMP technology
Car navigation systems, which are now indispensable as in-vehicle devices, have evolved from convenient devices used to provide guidance about routes to informational devices that give drivers not only entertainment information but also a sense of security and peace of mind. As these systems continue to evolve, demand grows for improvement of CPU performance. That's why NEC Electronics developed the NaviEngine multicore platform, the first system LSI chip to use a symmetric multicore processor (SMP) (*2) for car navigation systems. NaviEngine has brought to reality not only astoundingly high performance, but also low power consumption and exceptional reliability—both of which are essential when it comes to in-vehicle devices. We interviewed Masayasu Yoshida, who was involved in the development of NaviEngine, about the steps leading to its development.
The reason for adopting a multicore processor system for car navigation systems
Around 2002, we decided to develop a system LSI device for car navigation systems that would act as the nucleus of in-vehicle information. We began by conducting a market survey in which we found that in-vehicle device manufacturers were looking for higher performance in the 1,000 to 2,000 MHz range, one digit higher than existing performance levels. However, we quickly realized that this would mean a proportional increase in power consumption, thereby making implementation in vehicles difficult. We therefore needed to find a way to somehow clear that hurdle and achieve low power consumption during operation with a built-in system. The use of multicore technology thus became absolutely imperative.
Multicore technology made its debut as part of the high-performance computing trend that began in the 1980s, and NEC bypassed other companies in the industry by conducting research on multicore technology over a span of more than 20 years. The MP98, a four-core processor for handheld devices that was released around 2000, had already achieved both high performance and low power consumption. We therefore decided to create a multicore product for car navigation systems based on this technology. Parallel processing of the multicore enabled optimization of power efficiency, and in 2007, we were finally able to achieve low power consumption of 5 watts and under, and high performance of 1,920 MIPS at a clock speed of 400 MHz.
Hardships faced due to the use of SMP
SMP technology was integral to the creation of a high-performance system LSI device. However, we faced great difficulties when it came to convincing our customers of this. When development first began, societal recognition of multicore processor technology itself was low, and many designers were skeptical. In reality, asymmetric multicore processors (AMP) (*3) were already being used in mobile phones and other such devices, but it was said that it would be difficult to convert single-core software to multicore software. However, SMP was unlike AMP in that it had the advantages of being easy to program and able to consume low power. At the time of the NaviEngine multicore's development, performance, software development and techniques for system LSI development were thoroughly discussed over the course of a year and a half. Making these accomplishments at a time when other companies were being passive in regard to multicore technology had given NEC Electronics a tremendous advantage.
Implementation of collaborative efforts
Collaboration with partner companies became a critical factor in the development of the NaviEngine multicore. MPCore, which was co-developed with ARM® Ltd., was used for the CPU. CPUs by ARM are widely used in mobile phones and other such devices, and can be used with a wide range of middleware and software development tools. In addition, thanks to the use of an SMP-compatible operating system, programming can be carried out regardless of the number of cores, and conversion of existing single-core-use software is possible. Moreover, since the SMP-compatible operating system can automatically select which CPU should be used, depending on the application or type of software, development can be conducted without being cognizant of the fact that there are multiple cores.
In terms of a graphics engine, the NaviEngine multicore is equipped with the SXG535, the latest graphics core from Imagination Technologies Ltd., a company that prides itself on having 2D and 3D graphics with the industry's highest performance. We also amassed a multitude of IP cores necessary for car navigation systems and were very fortunate to have the opportunity to work in collaboration with many of our partner companies. As for software development environments, eSOL Co., Ltd. quickly gave its approval for the use of a multicore processor, and there are plans to offer eSOL's eT-Kernel Multi-Core edition and more in the future.
Proper operation of evaluation samples on the first attempt and zero defects
At the time of these collaborative efforts, our ultimate goal was proper operation of evaluation samples on the first attempt. Since a great deal of time was needed by our partner companies to carry out software development, it was imperative that our evaluation samples be capable of operating on the very first try. And because there were so many newly developed technologies being incorporated into the NaviEngine multicore, it would have been almost a miracle for it to operate properly on the first attempt.
It was also absolutely imperative that there be no defects when it came to in-vehicle-use semiconductors. We used design for testing (DFT) techniques for the purpose of failure detection and were just as resolute about achieving zero defects as we were about reaching the level desired for engine control. Even after release of the NaviEngine multicore to the market, we have remained and will continue to remain committed to our goal of zero defects.
The evolution of NaviEngine
Because electronic information devices aimed at providing convenience, comfort and safety in car navigation systems will continue to become more and more advanced in terms of performance, the NaviEngine multicore will continue to evolve. For example, by advancing from a 90-nanometer (nm) process to a 55 nm process, we can achieve lower power consumption while simultaneously meeting the needs of our customers, for example, by increasing the number of cores or by selecting additional functions with which NaviEngine can be equipped.
Our customers can look forward to the continued evolution of the NaviEngine multicore.
Notes(*)
- As of October 2007, according to an in-house survey
- Symmetric multicore processor (SMP)
This is a symmetric multicore processing technology for which specific roles are not assigned to any of the CPU cores and one program is processed by multiple cores. - Asymmetric multicore processor (AMP)
This is an asymmetric multicore processing technology for which each CPU core is assigned a specific role and programs are processed separately.
NaviEngine and IMAPCAR are registered trademark of NEC Electronics Corporation in Japan and other countries.
ARM11 and MPCore are trademarks of ARM Limited in Japan, Europe, the U.S. and other countries.
Experiencing multicore technology through a demonstration
Demonstration by a developerFour screens are displayed on the monitor shown. Top left, playback of a Windows Media® video; top right, high-resolution 3D racing image graphics created using the SGX535 graphics engine; bottom left, white line recognition using image recognition middleware; bottom right, the Windows® CE desktop screen is operated simultaneously as an operating system. (Note that the CPU utilization rate is displayed in the middle of each screen to showcase the use of multicore technology.)
260KB)