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Volume 72 (Oct 29, 2007)
Summary of NEC Electronics Papers Presented at the 2007 EOS/ESD Symposium (3/3)
A Low-Leakage SCR Design Using Trigger-PMOS Modulations for ESD Protection
We have developed a silicon-controlled rectifier (SCR)-type electrostatic discharge (ESD) protection circuit that achieves low leakage current together with low trigger voltage. Incorporating a P-channel MOSFET in the trigger element, the circuit can be adapted to a wide range of applications by modifying the structure of the PMOS logic.
As VLSI technology evolves toward smaller features, ESD protection circuits must also be downscaled, and this requires reducing the parasitic capacitance and leakage current levels. While progress has been made toward reducing the size and capacitance of SCR-type protection circuits, there is a tradeoff between reducing leakage current during normal operation and reducing trigger voltage when ESD events occur, and it is very difficult to reconcile the two. In this work, NEC Electronics has developed an SCR-type ESD protection circuit that satisfies both low leakage current and low trigger voltage by using a PMOS trigger element (Figure 1).
Leakage current of the ESD protection circuit during normal operation is determined by the cross-point between SCR PNP base current (IPNP) and the PMOS trigger element subthreshold current (IPMOS) (Figure 2). In the new ESD protection circuit, the PMOS trigger element is connected in such a way that its source potential is less than the gate and back-gate potential. The resulting drop of several tens of millivolts (mV) between the PNP emitter and base effectively reduces the subthreshold current of the PMOS trigger element by an order of one decade. As a result of this effect, the leakage current is dramatically reduced.
Positive ESD stress conditions with respect VSS are most severe during ESD events, but under these stress conditions the PMOS trigger element's gate voltage (VGS) is lower than the threshold voltage (VTH) due to the floating potential of VDD, so PMOS channel current readily flows (Figure 3). By optimizing the design parameters of all elements to ensure SCR triggering by this channel current, we have greatly reduced the ESD protection circuit's trigger voltage.
Based on test implementations in a 65-nanometer (nm)-fabricated system LSI chip, the ESD protection circuit achieves a leakage current of less than 0.1 pico-ampere (pA) and a trigger voltage of 1.8V. In a test chip, the ESD protection circuit also achieves excellent ESD performances of 5.5 kilovolts (kV) in the human body bodel (HBM) test and over 300V in the machine model (MM) test.
NEC Electronics is committed to making further progress in the development of system LSI chips incorporating SCR-type ESD protection circuits.
From engineer
Core Development Division (Left)
Mototsugu Okushima, Assistant Manager,
Core Development Division (Right)
This new SCR design technique was discovered in developing high-performance ESD protection circuits for serializer-deserializer (SerDes) ICs that are typically used in computer buses and other applications. A shortcoming of conventional SCR-type ESD protection circuits has been their inability to reduce leakage current, but we have now come up with a practical design solution using a PMOS trigger element that reduces leakage current while at the same time reducing the trigger voltage. We are now following up with a practical implementation of the design approach that can be incorporated in a wide range of semiconductors. In collaboration with other interested divisions and departments in the company—LSI design, process technology, reliability and quality control, and many other divisions—we plan to continue work on ESD protection devices that contribute to improved reliability and performance of system LSI chips.
Volume 73
