Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.
Volume 69 (July 26, 2007)
Summary of NEC Electronics Papers Presented at the 2007 Symposia on VLSI Technology and Circuits (4/5)
Highly Efficient Stress Transfer Techniques in Dual-Stress Liner CMOS Integration
By effectively exploiting stress-liner nitride-film stress, an innovative, NEC Electronics has developed a double-thinned sidewall structure that markedly improves transistor drive current and adhesion reinforcement, enabling fabrication of CMOS transistors that are cost-effective yet deliver high performance.
Continued evolution of the ubiquitous network society fuels an insatiable demand for very high-speed system LSI chips that are power thrifty and cost-efficient. CMOS technology is a proven solution for implementing transistors that are cost-effective yet deliver high performance. However, NEC Electronics has developed an innovative double-thinned sidewall structure and adhesion reinforcement technique that significantly boost transistor drive current by reinforcing the stress of stress-liner nitride film. By continuing to use common conventional material in the form of nitride film rather than introducing an exotic new material, we successfully held down costs while maintaining high performance.
There are several key advantages of this new architecture: the stress from stress-liner nitride film is efficiently transferred to transistors by a unique, thinned L-shaped sidewall structure, on-resistance caused by the piezoresistance effect is markedly reduced, and drive current is improved. As illustrated in Figure 1, we developed a novel process that we applied in the trial fabrication of test devices. In the process, gate-electrode sidewalls forming the source-drain electrode are implemented as a double, disposable sidewall spacer that is subsequently removed to transfer stress to the stress-resistant channel region. Another problem arises from the tendency of stress-liner nitride film to peel as a result of its own internal stress. We solved this issue by developing an adhesion reinforcement technique (Figure 2) that prevents relaxation of stress by sandwiching the interface between adhesion layers.
When comparing the performance of the new transistor with a thinned L-shaped sidewall structure shown in Figure 3 against a conventional transistor, we found that the new device showed a 6% improvement in MOSFET Ion current and a 10% improvement in channel conductance. Figure 4 shows device performance with the adhesion reinforcement technique applied. One can see that adhesion at the interface is significantly improved when sandwiched between oxide film or thin low-stress silicon-nitride film. Robustness against peeling is markedly improved, and the improved Ion current effect is especially striking in MOSFETs using compression silicon-nitride film.
Compared to a conventional device, MOSFET Ion current is improved by 6% and channel conductance by 10%.
(L) Peeling resistance is improved, and (R) Ion current in MOSFETs is improved by 7%.
With this device architecture and fab processing that compensate for high stress, we succeeded in exploiting the full potential of conventional nitride film. As the ubiquitous network society continues to evolve, NEC Electronics remains committed to the development of cost-efficient, high-performance transistors for very high-speed power-thrifty system LSI chips.
