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Volume 69 (July 26, 2007)
Summary of NEC Electronics Papers Presented at the 2007 Symposia on VLSI Technology and Circuits (3/5)
A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node
A cost-effective CMOS platform has been developed that monolithically integrates low-power transistors for both standby and standard operation in mobile devices. Cost-effective yet high-performance integrated transistors are implemented using hafnium to control the work function.
To extend the battery life of battery-powered mobile devices, we have seen growing demand in recent years for a low-cost integrated solution that combines two kinds of transistors: a low-power transistor for standard operation and a low-power transistor for standby mode. Generally the supply voltage must be reduced to hold down transistor power consumption in standard operation, but this also reduces the transistor current drive, which slows down the operation of the circuit. One can obtain high drive current with a low supply voltage by reducing the thickness of the gate dielectric film, but this can increase leakage current, which causes the power consumption in standby mode.
The only way to achieve a high-performance LSI chip for this type of application has been to integrate two kinds of transistors—a low-power transistor with thicker gate dielectric film for standby mode and a low-power transistor with thinner gate dielectric film for standard operating mode—but this degree of complexity drives up manufacturing costs. To address this challenge, NEC Electronics first developed a cost-effective way to monolithically integrate low-power transistors for both standard and standby operation using hafnium for the gate dielectric film, and also developed a cost-effective CMOS platform for the 45-nanometer (nm) node that increases drive current based on a new gate dielectric film deposition method.
As one can see in Figure 1, we developed a streamlined ion implantation processing method that could be applied in common to all four types of transistors used in the application: low-power core logic transistors for standard and standby operation, and transistors for input and output. More particularly, we exploited the hafnium-based work function control (*1) to achieve shared ion implantation processes for adjusting threshold voltages.
Moreover, as gate widths are reduced, this causes threshold voltages to also decline, a phenomenon known as the reverse narrow-channel effect. This is caused by the diffusion of channel impurity ions into shallow trench isolation (STI) (*2) features. We found that this could be prevented using a hafnium-based work function control to reduce the concentration of impurity ions in channels to produce transistors that are very robust against the reverse narrow-channel effect (Figure 2).
We also significantly improved channel mobility and drive current by optimizing the gate dielectric film formation processing (Figure 3).
Leveraging these technologies, NEC Electronics continues to make remarkable progress in developing very high-speed power-thrifty system LSI devices for a wide range of applications—from mobile devices to networks.
Notes(*)
- Work Function
The difference in intrinsic potential between the gate electrode and silicon substrate
- Shallow Trench Isolation (STI)
Deposition of silicon dioxide to prevent electrical current leakage between adjacent transistors
