Please note that JavaScript and style sheet are used in this website,
Due to unadaptability of the style sheet with the browser used in your computer, pages may not look as original.
Even in such a case, however, the contents can be used safely.
Volume 69 (July 26, 2007)
Summary of NEC Electronics Papers Presented at the 2007 Symposia on VLSI Technology and Circuits (1/5)
The "2007 Symposia on VLSI Technology and Circuits"—widely recognized as premiere conferences for presenting research results on the latest device, process, and circuit-related developments—were held this year at the Rihga Royal Hotel in Kyoto, Japan, from June 11 to 16, 2007. Here we will introduce the papers presented by NEC Electronics in collaboration with NEC Corporation.
VLSI Symposia Overview
The VLSI Symposia is a major conference on semiconductor technology, along with the International Electron Devices Meeting (IEDM) and the International Solid-State Circuits Conference (ISSCC). VLSI Symposia consists of two separate events: the VLSI Technology Symposium that focuses on device and process-related themes, and the VLSI Circuit Symposium that focuses on circuit-related themes. Along with technical sessions, the Symposia also included three one-day short course lectures: "Outlook for 32 nm CMOS Logic and Memory Technologies" at the VLSI Technology Symposium and "Design for Variability in Logic, Memory and Microprocessors" and "Advanced Topics on Multi-Standard Wireless Transceiver RFIC Designs" at the VLSI Circuits Symposium.
Papers Presented by NEC Electronics
Nine papers from NEC group were selected for presentation at the two symposia: five for the VLSI Technology Symposium and four for the VLSI Circuits Symposium. NEC Electronics researchers were engaged in four of the above: one solely by NEC Electronics researchers, and three in collaboration with researchers from NEC Corporation. Here we will describe the content of these four papers.
<<Paper Titles>>
- Session 3A-1: Variability in SRAM
- SRAM Critical Yield Evaluation Based on Comprehensive Physical / Statistical Modeling, Considering Anomalous Non-Gaussian Intrinsic Transistor Fluctuations
- This is a technology for physically estimating random fluctuations in submicron devices and precisely incorporating the estimated random fluctuations in circuit simulation designs. This enables highly accurate estimates of the stability of circuit characteristics (for example, for an SRAM cell) prior to mass production.
- Session 10A-2: CMOS Platform/Integration Technology
- A Cost-Effective LOP/LSTP Integrated CMOS Platform Utilizing Multi-Thickness SiON Gate Dielectrics with Hafnium for 45-nm Node
- A cost-effective CMOS platform has been developed that monolithically integrates low-power transistors for both standby and standard operation in mobile devices. Cost-effective yet high-performance integrated transistors are implemented using hafnium to control the work function.
- Session 12A-4: Advanced CMOS Devices
- Highly Efficient Stress Transfer Techniques in Dual-Stress Liner CMOS Integration
- By effectively exploiting stress-liner nitride-film stress, NEC Electronics developed an innovative double-thinned sidewall structure that markedly improves transistor drive current and adhesion reinforcement, enabling fabrication of CMOS transistors that are cost-effective yet deliver high performance.
- Session 9-1: Low Power Wireless Communication
- Development of Fundamental New Technologies Enabling Further Digitization of Wireless IP Cores
- We have developed key technologies promoting digitization of wireless intellectual property (IP) cores that facilitate easy embedding of IP cores in system LSI chip while reducing the cost and power consumption of wireless devices.
631KB)