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Volume 67 (July 02, 2007)

SMAFTI™: New Packaging Technology Enables Evolution of Mobile Devices

At the 13th Symposium on Microjoining and Assembly Technology in Electronics (MATE 2007) in February 2007, NEC Electronics received the Encouragement Award for Research and Development for a paper titled, "Development of BGA Attach Process with High-Density SiP Technology SMAFTI." Given in recognition of technologies showing exceptional scientific and technological future potential, the award had also been presented to NEC Electronics seven years earlier. SMAFTI (SMArt chip connection with Feed-Through Interposer) is an innovative system-in-package (SiP) technology supporting 3D interconnects with approximately a 60-micron gap and 50-micron pitch between logic and memory devices. This technology permits much faster data transfers between processor and memory chips as well as larger capacity memory, thus enabling the high-resolution display of graphics in cellular phones and other high-end consumer devices. We asked the engineers who developed SMAFTI to give us some insight into its development background and describe some key features of the award-winning technology.

Q: What were the circumstances leading to the development of SMAFTI?

Today system-on-a-chip (SoC) technology is widely used to integrate required functions and components for a particular application—memory and logic ICs—into a single integrated circuit (chip). Drawbacks of the SoC approach are the relatively high development cost and the chip's limited memory capacity.

Since 1999, NEC Electronics had thus been working on a new packaging approach that would meet the requirements of mobile devices—that is, would support more advanced functions and capabilities, high-speed data transfer rates and larger memory capacity. At the same time, our customers were calling for a low-cost, high-density packaging solution, which motivated us to launch a full-scale initiative to develop a new SiP technology that would achieve these goals.

We knew from the outset that we had to figure out a way to enhance the memory bus performance in order to increase the data transfer rate between the processor and memory. Chip-on-chip (CoC) packages achieve higher data transfer speeds using microbump interconnection technology, but the chip size restriction makes it extremely difficult to increase the memory capacity. The conventional SiP approach accommodates larger memory capacity by stacking the processor and memory chips in a single package, but the data transfer speed is limited by wire-bonding interconnections. Essentially, we needed to find a solution that combined the strengths of both of these approaches: the high-speed data transfer of CoC packages and the larger memory capacity of conventional SiPs. We came up with all kinds of novel package designs and went through endless trial-and-error experiments.

It was during this period that Yoichiro Kurita, with his considerable expertise in mass production, joined our development team. We wasted no time seeking his advice, and Kurita observed that "first and foremost, we had to come up with an all-new type of package." We were looking for a bold new approach that was not fettered by existing concepts. Eventually, he came up the novel 3D structure package that was the model for SMAFTI, and indeed this proved to be precisely the package that we had in mind.

Q: How did you conceive the idea for the new 3D structure package?

NEC Electronics already had an excellent grasp of all of the key technologies involved, including microbump forming, copper interconnect and packaging technologies. I am sure that all my previous work experience involving mass production also paid off, but the archetype for the 3D structure just came to me naturally as I investigated various aspects of the project. I should also admit that, when I first came up with the idea for the new 3D structure, I was not at all sure whether it was technologically feasible.
It was apparent that the key to successful implementation would be the development of an ultra-thin feed-through interposer (FTI). We overcame this first hurdle by developing a 15-micron-thick FTI based on superconnect technology,^*1 which uses 15-micron-wide copper wiring and a 7-micron-thick polyimide resin. The interposer interconnects processor and memory chips with an extremely narrow wiring pitch of only 50 microns, and also provides leads from the processor to external pins. The interposer also supports stacked memory using through silicon vias (TSVs), and can support up to eight memory chips and one processor chip integrated in a single package.

Q: What are the main differences between conventional SiP technology and high-density SiP technology?

There are a number of significant differences. First, they are structurally quite different. In conventional SiP technology, the imposer or circuit board is much thicker, so it is practically impossible to implement narrow-pitch interconnections. And since conventional SiP devices use wire-bonding interconnections, there is a limitation to speed up the data transfer rate. By contrast, SMAFTI does not use wire-bonding interconnects and represents an all new type of 3D structure package. The differences are very apparent if you compare SMAFTI to conventional SiP or CoC packages.

The performance of the new 3D structure is far superior to that of the conventional SiP approach. The memory bus performance in particular is much enhanced by using microbump interconnects between the processor or other logic chip and the memory chips instead of wire-bonding interconnects. The net effect is a markedly faster data transfer rate. The new structure also readily accommodates larger memory capacity that would be very difficult with the CoC approach.

Another major difference from conventional packaging schemes is that most of the assembly process can be done by the wafer-level processing. In other words, final packaging functions are implemented without a high-cost package substrate. And because the structure is simpler, the assembly processing takes less time. This not only improves the quality of the product, it also results in lower cost and more efficient production.

Q: What were some of the challenges you overcame in developing the new packaging technology?

Considerable time was spent developing and fine-tuning SMAFTI assembly processes. For example, the BGA solder balls are mounted on just a resin wafer after the silicon wafer has been removed, so we had to contend with a significant amount of warpage due to thermal expansion mismatch. We tried many resin material combinations, repeatedly fine-tuned the resin molding conditions and optimized the solder ball mounting equipment. All of these efforts paid off, so now we can batch-mount 42,604 solder balls at a time with a ball-missing failure rate of only 170 parts per million (ppm). The reflow process with around 230°C also presented a challenge, but by carefully optimizing the process conditions, we obtained excellent results and the solder balls do not stick together. At the board level, we came up with a number of innovations ensuring greater robustness and long-term reliability.

Q: How will customers benefit from the new packaging technology?

The new SMAFTI packaging technology provides high-speed data transfer rates and larger memory capacity at lower cost. This means better performance for high-end cellular phones and a host of other consumer electronic devices, and also contributes to shorter manufacturing cycles and lower costs for customers.

Thank you for your insights!

Working toward greater diversity of electronic devices and more advanced capabilities, NEC Electronics is committed to development and provisioning of products that achieve higher-quality video processing in cellular phones and other consumer electronic devices.


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