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Volume 62 (Dec 08, 2006)

Defeat Electrostatic Damage! New Techniques for Protecting Against Electrostatic Discharge in 90-nm Processes and Beyond

The 28th international Electrical Overstress and Electrostatic Discharge (EOS/ESD) Symposium was held September 10-15, 2006, in Tucson, Arizona, USA by the Electrostatic Discharge Association, the world's leading authority on electrostatic/electromagnetic problems in electronic devices and components, their solutions and related research. This article describes the research results presented by NEC Electronics at this year's EOS/ESD Symposium.

The gate oxide of a transistor becomes increasingly thin (below 1.6 nm), especially in 90 nm and smaller generations as semiconductor dimensions are scaled down. This thinness results in a remarkable drop of a transistor's ESD robustness (Figure 1). At the same time, there has been a trend toward multi-power-domain SoCs in which power domains are separated to improve noise characteristics in the high-speed I/O and analog blocks that make up a multifunction LSI chip. Many LSI devices for mobile applications have also incorporated a multi-power-supply configuration separating 10 or more power domains to decrease power consumption while providing an efficient flow of power to the various function blocks. It is difficult, however, to establish ESD protection in the interface between such electrically separated power domains, and this has become a major issue of concern (Figure 2). In response to this problem, we have developed an ESD-protection design for 90 nm and beyond SoCs with multiple power domains. This design features (a) a contact-ballast (CTB) layout technique, a new type of ESD-protection device for each power domain, that increases ESD robustness between power domains and (b) an ESD protection circuit that senses and reacts to current flowing between GND buses at the time of an ESD event.

Figure 3 shows the CTB layout technique. Using contact resistance made up of vertically formed resistors, this new ESD protection device features reduced area and high performance. It achieves a level of ESD protection of 1.6 nm gate oxide, three times that of existing NEC Electronics devices for the same area.

We have also developed two types of an ESD protection circuit (ground current trigger) that senses and works to current flowing between different GND buses during an ESD event (Figure 4). In the first type of circuit, an NMOS transistor between GND buses functions as a protection device that senses the potential difference caused by current flowing between GND buses (1) during an ESD event and prevents voltage from rising (2) in the interface signal line (Figure 4(a)). In the second type of circuit, an NMOS transistor between GND buses functions as a trigger circuit for a thyristor protection device that provides a bypass between power domains (Figure 4(b)). This sensing function makes for low-voltage operation of the protection circuit and achieves an ESD robustness of 500V in the MM standard^*1 and 7,000V in the HBM standard^*2, which is 2.5 times that of existing NEC Electronics protection circuits at 1/7 the area.

The new CTB layout technique has already been applied to 90 nm processes and the plan is to apply the above ESD protection circuits to 55 nm processes. NEC Electronics will continue in its efforts to develop ESD protection techniques for low-power and multi-function SoC LSI devices.

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