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Volume 58 (Aug 23, 2006)
Overview of Papers Presented at IITC 2006 (2/3)
Highly Reliable Interface Control Technology by using Self-Aligned CuSiN Process with Low-k SiC Barrier Dielectric (k=3.5) for 65 nm Node and Beyond
A highly reliable interface control technology has been developed based on a combination of self-aligned CuSiN processing and low-k barrier dielectric (k=3.5). The technology reduces interconnect capacitance while improving device reliability.
An enormous amount of effort has gone into reducing the dielectric constant of dielectric interlayers to increase the operating speed of system LSI circuits. But reducing the dielectric constant of the diffusion barrier dielectric causes reliability problems due to surface oxidation on Cu interconnects and reduction of breakdown voltage between Cu interconnects. For these reasons, higher dielectric constant materials have continued to be used as a diffusion barrier dielectric and practical efforts to reduce the dielectric constant have been stymied.
Now we have discovered an effective way to stop this oxidation and improve the breakdown characteristics between copper interconnects for current 65 nm and smaller-feature CMOS logic circuits by forming a self-aligned CuSiN layer on the surface of the interconnects and applying a nitride treatment to the dielectric surface. By leveraging a technology that does not diminish in reliability even when forming a low-k diffusion barrier dielectric, we have achieved a highly reliable interface control technology.
Figure 1 shows the self-aligned CuSiN process and low-k SiC deposition process flow. Before depositing the low-k diffusion barrier dielectric of SiC, a layer of CuSiN is formed on the surface of the copper interconnect by plasma deoxidization and plasma SiH4 treatment followed by the nitrogen-containing plasma step. The dielectric surface is also nitridated at the same time. After this step is completed, the low-k SiC barrier dielectric is deposited.
Figures 2-5 show the results of applying this technology to a two-layer interconnect structure with SiOC-based single damascene. The interconnect capacitance and leakage current have been reduced while the yield has been improved.
The reliability results presented in Figures 6-7 reveal that the via electromigration and interlevel dielectric breakdown characteristics have been significantly improved. Also, after comparing performance results with a conventional barrier dielectric pretreated with NH3 plasma, we found that introducing Si to the surface of the copper interconnect in advance was effective in suppressing CuO (Figure 8). We also verified the nitrization of the dielectric surface beneath the SiC layer (Figure 9).
This technology makes it possible to achieve both a lower dielectric constant and higher reliability at the same time. NEC Electronics plans to pursue this promising research to achieve even more reliable designs for 65 nm node features and beyond.
* The work was done in cooperation with Novellus Systems, Inc.
