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Volume 54 (Mar 29, 2006)

Introduction to papers presented at ISSC 2006 (3/3)

Re-definition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit

Redefining the SRAM writing margin has enabled the lowest value to be estimated. This makes it possible to significantly reduce development time for SRAM devices.

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With decreases in supply voltage (V_DD) and increases in V_th variation of the transistor accompanied by the geometric scaling, not only the reading margin but also the writing margin greatly deteriorates in SRAM devices above the 65-nm node. The worst value of the reading margin can be estimated easily under the conventional definition. The worst value of the writing margin, however, cannot be estimated from a low sample number under the conventional definition; SRAM development therefore takes a long time.

With the conventional definition, when DC characteristics of the inverters of the internal circuit are calculated, the word-line (WL) terminal is fixed at power-supply voltage V_DD, and if the writing margin does not become extremely low, V_th variation of the transistor cannot be expressed as the variation of the writing margin. As a result, it has been necessary to measure huge samples to estimate the worst value of writing margin.

With this background in mind, at NEC Electronics and NEC Corporation, we have redefined the writing margin to be estimated from a small number of samples (see Figure 1). In the measurement of inverter 1 with conventional definition, the WL terminal is fixed at power-supply voltage V_DD, and node V2 is taken as the input terminal. With our new definition, the voltage level of V_OL^*1 is input to node V2 and the WL terminal is taken as an input terminal in the measurement of DC characteristics of the inverter 1. Our new writing margin is defined as V_DD-V_WL, where V_WL is the voltage of WL that makes the output voltage of inverter 1, V1, equal to the logical threshold voltage of inverter 2, V_th2. As a result, the relationship between writing margin and V_th variation of access transistor N3 under all conditions becomes linear, and the worst value of the writing margin can be calculated.

With this new definition of writing margin, not only the worst value of the writing margin can be calculated from a small sample number but also the effects of process variation and operating environment (temperature, power-supply voltage, etc.) can be quantified. As a result, the development time needed for SRAM can be significantly shortened. On top of that, the limit to scaling down of SRAM from now onward can be predicted. This new definition will also be useful for quantifying the effect of the already-proposed "writing-assist" method and for research on circuit technology for further extending the scaling limit.

We have developed a circuit that applies this new definition in observing the writing margin (see Figure 2). This circuit is composed of three inverters and an operational amplifier. The operational amplifier controls gate voltage V_WL of N3 of inverter 1 so that inverter 1 outputs V_th2. V_th2 is the logic threshold value of inverter 2, and inverter 3 outputs voltage V_OL^*1 to inverter 1. Because this circuit outputs the writing margin as a voltage value, the circuit is very useful to control SRAM power-supply voltage optimally for the conventional writing-assist method. It can also be used as a process-check circuit.

Aiming to provide, without delay, a memory that operates at high speed and low power (voltage) in response to device scaling-down, NEC Corporation and NEC Electronics are developing a beyond-65-nm-generation SRAM that applies this newly defined writing margin.

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