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Volume 45 (Aug 05, 2005)
Overview of Papers Presented at 2005 Symposia on VLSI Technology and Circuits (3/4)
Ultra-low-energy-consuming 65 nm CMOS technology using HfSiON gate dielectric layer and substrate bias effect (Session 12A-3)
Through consolidation of the communications infrastructure and diversification of information content in recent years, the amount of data being processed on mobile data devices has continued to increase. With these developments has come a demand for controlling power consumption while increasing operating speeds in system LSI chips that, as a group, play a very important role. Until now, this demand has been met by making the transistor's gate-oxide layer thinner and its operating voltage lower. However, any further reduction of the gate-oxide layer, which is already approaching physical limits, will result in a sudden increase in gate leakage current. Furthermore, decreasing the voltage without sacrificing transistor drive capability is accompanied by an increase in off-leak current. By employing a high-k layer with HfSiON (Hafnium-nitride silicate) in the gate dielectric layer, and reducing the off-leak current using substrate bias control, NEC has developed an effective transistor structure. Normally, when using an HfSiON layer for the gate dielectric layer, the transistor threshold voltage increases due to the Fermi-level pinning phenomenon*1. This effect is particularly large in P-channel transistors, and it has not been possible to achieve high enough drive capability. With this development, we have optimized the channel profile and halo structure*2 for a transistor using HfSiON (Figure 4). As a result, we have been able to suppress the gate-leak current and attain a transistor drive capability not achievable earlier (Figure 5).
With respect to the earlier, higher-threshold voltage transistors, when substrate bias control was used, the leakage current (IGIDL) between the drain electrode and substrate increased, which increased the off-leak current. With use of the HfSiON layer together with the optimized transistor structure, not only can the threshold voltage be set as desired, but IGIDL) can be suppressed using a substrate bias voltage that allows the off-leak current to be reduced (Figure 6).
Using these techniques, we plan to increase the performance of mobile information devices without sacrificing battery life. At NEC Electronics, we are advancing the implementation of this technology to realize higher-performance system LSI chips without increasing energy consumption.
*1 The change in the work function of the gate electrode due to the Si-Hf junction/bond at the gate electrode/dielectric interface
*2 A structure that introduces impurities around the source-drain edge of the transistor channel in order to make fine improvements to the transistor characteristics
