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Volume 45 (Aug 05, 2005)
Overview of Papers Presented at 2005 Symposia on VLSI Technology and Circuits (2/4)
Molecular-pore inter-layer, low-k film promises successful multi-layer copper interconnects for 45 nm LSI chips (Session 2-4)
NEC has developed a new, low-dielectric-constant dielectric film and copper-interconnect structure that can be used in 45 nm CMOS logic circuits to increase circuit operating speeds. The porous SiOCH film has a molecular-pore stacking (MPS) structure and relatively low dielectric constant (k=2.4) that effectively achieves a multi-layer interconnect structure when combined with low-resistance copper interconnects. The interconnect pitch (sum of the width of interconnects and the spacing between them) is 140 nm and the via holes connecting the interconnects on different layers are 70 nm, half the size of those in the 90 nm process currently in production. These pitch sizes are promising options for the very high densities being required for multi-layer interconnects in each new generation.
The MPS-SiOCH film is created by plasma polymerization of six-member, ring-vinyl siloxane that has a molecular vacancy. The plasma polymerization process converts the k value into the 2.2 to 2.5 range, while maintaining the same mechanical strength (modulus of elasticity) as in the 65 nm process. This modulus results from the strength of the six-member ring structure that forms the backbone of the film (Figure 1). The photograph below shows a TEM cross-section of a hybrid structure that uses this MPS-SiOCH film between interconnects on the same layer, and also shows the normal SiOCH film between interconnects on different layers (Photo 1).
Porous, low-dielectric films such as MPS-SiOCH tend to become oxidized, increasing their dielectric constant, when exposed to oxygen plasma during processes such as photo-resist ashing. Therefore, NEC developed a hard mask process that avoids exposure while creating the trenches of the interconnects. Compared to the 65 nm process, the interconnect area used is reduced by 16% (Figure 2). Leakage current, caused by contact between adjacent interconnects and the dielectric breakdown of electrical field strength, which can be concerns with fine interconnects, is in the same range as for the 65 nm process (Figure 3). The electrical resistance of the via holes, which connect different interconnect layers, is about 13.5 ohm. Table 1 summarizes these various characteristics.
These MPS-SiOCH/Cu-based multi-layer interconnects with 140 nm pitch can be applied to a wide range of products, from LSI chips for high-end microprocessors to digital consumer products and low-power 45 nm CMOS LSI devices. NEC will continue to develop 45 nm LSI interconnect technology in collaboration with NEC System Device Laboratories, with the goal of bringing the technology to mass production more quickly.
