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Volume 22 (July 21, 2004)

The Challenges and Passion Behind the Creation of the V850 Series (1/2)

Part 1: Creating the world's first 32-bit single-chip microcontroller

In the midst of an age of major changes in the microcontroller industry

In December 2003, the shipping volume of products equipped with 32-bit V850™ microcontroller cores reached the 300 million mark. This feat was accomplished approximately seven and a half years after the market launch of the original V850 Series single-chip microcontroller in April 1996. Products incorporating V850 cores are currently manufactured by more than 500 companies around the world. Although the V850 Series now plays an active role in a variety of applications ranging from consumer devices to automobile control devices, Hiroaki Kaneko looks back on the setbacks faced during the development of the world's first RISC 32-bit single-chip microcontroller 11 years ago and describes the time as one in which those involved were "groping blindly in the dark."

At the time, the industry was in the midst of major changes; microcontrollers were making the transition from 16-bit to 32-bit and from Complex Instruction Set Computer (CISC) to Reduced Instruction Set Computer (RISC). NEC Electronics (then NEC), the top supplier of 4-, 8- and 16-bit single-chip CISC microcontrollers with an extensive product line, was even at the cutting edge of development for 32-bit RISC. In fact, the company had already successfully developed the original 32-bit V810 RISC microprocessor. However, although the V810 had been highly rated by the company's microprocessor customers, it was evaluated much more critically by single-chip microcontroller customers-even when it came to cord size. To increase RISC performance, it was necessary to use a larger cord size than that employed for CISC. For single-chip microcontrollers, however, increasing cord size to improve performance was not accepted as a legitimate reason.

Proposing mass production of 32-bit RISC for the next generation

In December 1992, Kaneko took an unexpected trip to California to visit NEC Electronics' largest 78K/III Series 16-bit microcomputer customer-a hard disk drive manufacturer-and make a presentation focused on next-generation products. Although it had already been decided that the 78K/VII Series would be deployed as the follow-up to the 78K/III Series, the customer was demanding higher performance. Therefore, Kaneko decided to make his presentation on the V810-based 32-bit RISC microprocessor that had just been unveiled that year. In his presentation, he proposed that the next generation in microcontrollers would be led by the V810-based 32-bit RISC and that mass production would be available. However, it turned out that the customer had DSP in mind. This meant that his presentation was for a completely different product plan. Revealing his true feelings, Kaneko comments, "If I think back on it now, what I tried to do was nearly impossible. But there was nothing else I could do and I thought it would be alright." His read of the situation, however, proved to be off the mark.

Kaneko says in retrospect, "I was not at all up to speed on hard disk control software." That is to say, he had absolutely no idea what it was the customer actually wanted to do. Although he was at a loss and filled with regret, Kaneko knew that if he were to give up, it would render his trip to California completely meaningless. He then decided to ask the customer company for its program source code. Ordinarily, companies do not allow program source code to be taken off the premises, so it was only natural that the customer was hesitant about complying with this request. Kaneko, however, was persistent. Under the conditions that the customer would not provide any explanation or answer any questions, Keneko received the source code. The program was written in assembly language and measured approximately 3,000 lines in length. Kaneko then found himself faced with the task of using actual data to prove to the customer that higher performance could be achieved using a 32-bit RISC to read and execute the company's own highly specialized program. Although Kaneko was under an incredible amount of pressure, his curiosity as to whether or not the 32-bit RISC would be capable of reading the source code for the customer's actual products won out above all else.

Going back and forth between architecture creation and test programming

The single-chip RISC microcontroller development team was launched on January 14, 1993. Setting the speed and program size of the 78K/III Series 16-bit microcontroller that had been used up until that time at 100, the team quantified what the speed and program size would be for the 32-bit RISC and then decided to submit a proposal to the customer. Hideki Sugimoto, the youngest member of the team, was put in charge of the main design. Although he was soon to be married, he knew he shouldn't get too caught up in his wedding plans. Sugimoto devoted himself to his work and dealt with personal matters on his occasional day off, making for a rather tough schedule. Sugimoto laughingly comments, "I was still rather young and I don't really think that it was too much of a hardship for me."

Hard disk control software can be divided into two categories: system control and servo control. Although the servo control portion of the source code obtained from the customer was only a several-hundred-line program, it was extremely specialized. It was from this program that the development team analyzed the algorithm. Since servo control necessitates advanced digital signal processing, a DSP function would be required. The team then prepared a specialized multiplier capable of computing with just one clock as hardware: one set of instructions for DSP computing and 32 resistors (work domain) for use during computing. This made it possible to broaden the work domain despite the fact that the computing power would be equivalent to or greater than that of a 16-bit DSP. One of the particularly difficult tasks faced by the team was the improvement of interrupt response speed. Since the servo is activated by interrupt, total performance will drop due to poor interrupt response even if computing power is high.

For system control, an architecture capable of boosting C language programming efficiency was adopted and an optimizing compiler was prepared. In addition, instructions for manipulating bit data stored in memory were prepared and plans worked out to ensure that the 32-bit RISC would be compatible with single-chip-specific applications.

It was now the end of February 1993. Approximately three months after obtaining the program source code and after much trial and error, the team completed the basic design. With this design, the performance index was 710% higher than that for the 78K/III Series and the cord size index reached the 95% level. Taking MHz into consideration as well, the speed was 10 times faster than that of the 78K/III Series, and the program size (ROM size) was equivalent to that of the said series. That is to say, utilization of this design would make it possible to offer a single-chip microcontroller with ten times the efficiency of the 78K/III Series at approximately the same cost.

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